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兆易創(chuàng)新GD32E230F4P6-GD32 ARM Cortex-M23 Microcontroller

兆易創(chuàng)新GD32E230F4P6-GD32 ARM Cortex-M23 Microcontroller GigaDevice Semiconductor Inc. GD32E230xx ARM? Cortex?-M23 32-bit MCU Datasheet General description The GD32E230xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM? Cortex?-M23 core. The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor delivers high energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier and a 17-cycle divider. The GD32E230xx device incorporates the ARM? Cortex?-M23 32-bit processor core operating at up to 72 MHz frequency with Flash accesses 0~2 wait states to obtain maximum efficiency. It provides up to 64 KB embedded Flash memory and up to 8 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC and one comparator, up to five general 16-bit timers, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, and an I2S. The device operates from a 1.8 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32E230xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. Device information Table 2-1. GD32E230xx devices features and peripheral list ? Part Number GD32E230xx ? K4U6 K6U6 K8U6 K4T6 K6T6 K8T6 C4T6 C6T6 C8T6 FLASH (KB) 16 32 64 16 32 64 16 32 64 SRAM (KB) 4 6 8 4 4 8 4 6 8 Timers General timer(16-bit) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) ? Advanced timer(16-bit) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) ? SysTick 1 1 1 1 1 1 1 1 1 ? Basic timer(16-bit) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) ? Watchdog 2 2 2 2 2 2 2 2 2 ? RTC 1 1 1 1 1 1 1 1 1 Connectivity ? USART 1 (0) 2 (0-1) 2 (0-1) 1 (0) 2 (0-1) 2 (0-1) 1 (0) 2 (0-1) 2 (0-1) ? ? I2C 1 (0) 1 (0) 2 (0-1) 1 (0) 1 (0) 2 (0-1) 1 (0) 1 (0) 2 (0-1) ? ? SPI/I2S 1/1 (0)/(0) 1/1 (0)/(0) 2/1 (0-1)/(0) 1/1 (0)/(0) 1/1 (0)/(0) 2/1 (0-1)/(0) 1/1 (0)/(0) 1/1 (0)/(0) 2/1 (0-1)/(0) GPIO 27 27 27 25 25 25 39 39 39 CMP 1 1 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 16 16 ADC Units 1

產(chǎn)品描述

GigaDevice Semiconductor Inc.
GD32E230xx
ARM® Cortex®-M23 32-bit MCU
Datasheet

General description

The GD32E230xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M23 core. The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor delivers high energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier and a 17-cycle divider.
The GD32E230xx device incorporates the ARM® Cortex®-M23 32-bit processor core operating at up to 72 MHz frequency with Flash accesses 0~2 wait states to obtain maximum efficiency. It provides up to 64 KB embedded Flash memory and up to 8 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC and one comparator, up to five general 16-bit timers, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, and an I2S.
The device operates from a 1.8 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32E230xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.

Device information

Table 2-1. GD32E230xx devices features and peripheral list

Part Number		GD32E230xx
		K4U6	K6U6	K8U6	K4T6	K6T6	K8T6	C4T6	C6T6	C8T6
FLASH (KB)		16	32	64	16	32	64	16	32	64
SRAM (KB)		4	6	8	4	4	8	4	6	8
Timers	General timer(16-bit)	4 (2,13,15,16)	4 (2,13,15,16)	5 (2,13-16)	4 (2,13,15,16)	4 (2,13,15,16)	5 (2,13-16)	4 (2,13,15,16)	4 (2,13,15,16)	5 (2,13-16)
	Advanced timer(16-bit)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)
	SysTick	1	1	1	1	1	1	1	1	1
	Basic timer(16-bit)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)
	Watchdog	2	2	2	2	2	2	2	2	2
	RTC	1	1	1	1	1	1	1	1	1
Connectivity	USART	1 (0)	2 (0-1)	2 (0-1)	1 (0)	2 (0-1)	2 (0-1)	1 (0)	2 (0-1)	2 (0-1)
	I2C	1 (0)	1 (0)	2 (0-1)	1 (0)	1 (0)	2 (0-1)	1 (0)	1 (0)	2 (0-1)
	SPI/I2S	1/1 (0)/(0)	1/1 (0)/(0)	2/1 (0-1)/(0)	1/1 (0)/(0)	1/1 (0)/(0)	2/1 (0-1)/(0)	1/1 (0)/(0)	1/1 (0)/(0)	2/1 (0-1)/(0)
GPIO		27	27	27	25	25	25	39	39	39
CMP		1	1	1	1	1	1	1	1	1
EXTI		16	16	16	16	16	16	16	16	16
ADC	Units	1	1	1	1	1	1	1	1	1
	Channels (External)	10	10	10	10	10	10	10	10	10
	Channels (Internal)	2	2	2	2	2	2	2	2	2
Package		QFN32			LQFP32			LQFP48

Part Number		GD32E230xx
		F4V6	F6V6	F8V6	F4P6	F6P6	F8P6	G4U6	G6U6	G8U6
FLASH (KB)		16	32	64	16	32	64	16	32	64
SRAM (KB)		4	6	8	4	6	8	4	6	8
Timers	General timer(16-bit)	4 (2,13,15,16)	4 (2,13,15,16)	4 (2,13,15,16)	4 (2,13,15,16)	4 (2,13,15,16)	4 (2,13,15,16)	4 (2,13,15,16)	4 (2,13,15,16)	5 (2,13-16)
	Advanced timer(16-bit)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)	1 (0)
	SysTick	1	1	1	1	1	1	1	1	1
	Basic timer(16-bit)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)	1 (5)
	Watchdog	2	2	2	2	2	2	2	2	2
	RTC	1	1	1	1	1	1	1	1	1
Connectivity	USART	1 (0)	2 (0-1)	2 (0-1)	1 (0)	2 (0-1)	2 (0-1)	1 (0)	2 (0-1)	2 (0-1)
	I2C	1 (0)	1 (0)	2 (0-1)	1 (0)	1 (0)	2 (0-1)	1 (0)	1 (0)	2 (0-1)
	SPI/I2S	1/1 (0)/(0)	1/1 (0)/(0)	2/1 (0-1)/(0)	1/1 (0)/(0)	1/1 (0)/(0)	2/1 (0-1)/(0)	1/1 (0)/(0)	1/1 (0)/(0)	2/1 (0-1)/(0)
GPIO		15	15	15	15	15	15	23	23	23
CMP		1	1	1	1	1	1	1	1	1
EXTI		16	16	16	16	16	16	16	16	16
ADC	Units	1	1	1	1	1	1	1	1	1
	Channels (External)	9	9	9	9	9	9	10	10	10
	Channels (Internal)	2	2	2	2	2	2	2	2	2
Package		LGA20			TSSOP20			QFN28

Memory map

Table 2-3. GD32E230xx memory map

Pre-defined Regions	Bus	ADDRESS	Peripherals
		0xE000 0000 - 0xE00F FFFF	Cortex M23 internal peripherals
External Device		0xA000 0000 - 0xDFFF FFFF	Reserved
External RAM		0x60000000 - 0x9FFFFFFF	Reserved
Peripherals	AHB1	0x5004 0000 - 0x5FFF FFFF	Reserved
		0x5000 0000 - 0x5003 FFFF	Reserved
	AHB2	0x4800 1800 - 0x4FFF FFFF	Reserved
		0x4800 1400 - 0x4800 17FF	GPIOF
		0x4800 1000 - 0x4800 13FF	Reserved
		0x4800 0C00 - 0x4800 0FFF	Reserved
		0x4800 0800 - 0x4800 0BFF	GPIOC
		0x4800 0400 - 0x4800 07FF	GPIOB
		0x4800 0000 - 0x4800 03FF	GPIOA
	AHB1	0x4002 4400 - 0x47FF FFFF	Reserved
		0x4002 4000 - 0x4002 43FF	Reserved
		0x4002 3400 - 0x4002 3FFF	Reserved
		0x4002 3000 - 0x4002 33FF	CRC
		0x4002 2400 - 0x4002 2FFF	Reserved
		0x4002 2000 - 0x4002 23FF	FMC
		0x4002 1400 - 0x4002 1FFF	Reserved
		0x4002 1000 - 0x4002 13FF	RCU
		0x4002 0400 - 0x4002 0FFF	Reserved
		0x4002 0000 - 0x4002 03FF	DMA
	APB2	0x4001 8000 - 0x4001 FFFF	Reserved
		0x4001 5C00 - 0x4001 7FFF	Reserved
		0x4001 5800 - 0x4001 5BFF	DBG
		0x4001 4C00 - 0x4001 57FF	Reserved
		0x4001 4800 - 0x4001 4BFF	TIMER16
		0x4001 4400 - 0x4001 47FF	TIMER15
		0x4001 4000 - 0x4001 43FF	TIMER14
		0x4001 3C00 - 0x4001 3FFF	Reserved
		0x4001 3800 - 0x4001 3BFF	USART0
		0x4001 3400 - 0x4001 37FF	Reserved
		0x4001 3000 - 0x4001 33FF	SPI0/I2S0
		0x4001 2C00 - 0x4001 2FFF	TIMER0
		0x4001 2800 - 0x4001 2BFF	Reserved
		0x4001 2400 - 0x4001 27FF	ADC
		0x4001 0800 - 0x4001 23FF	Reserved

Pre-defined Regions	Bus	ADDRESS	Peripherals
		0x4001 0400 - 0x4001 07FF	EXTI
		0x4001 0000 - 0x4001 03FF	SYSCFG + CMP
	APB1	0x4000 CC00 - 0x4000 FFFF	Reserved
		0x4000 C800 - 0x4000 CBFF	Reserved
		0x4000 C400 - 0x4000 C7FF	Reserved
		0x4000 C000 - 0x4000 C3FF	Reserved
		0x4000 8000 - 0x4000 BFFF	Reserved
		0x4000 7C00 - 0x4000 7FFF	Reserved
		0x4000 7800 - 0x4000 7BFF	Reserved
		0x4000 7400 - 0x4000 77FF	Reserved
		0x4000 7000 - 0x4000 73FF	PMU
		0x4000 6400 - 0x4000 6FFF	Reserved
		0x4000 6000 - 0x4000 63FF	Reserved
		0x4000 5C00 - 0x4000 5FFF	Reserved
		0x4000 5800 - 0x4000 5BFF	I2C1
		0x4000 5400 - 0x4000 57FF	I2C0
		0x4000 4800 - 0x4000 53FF	Reserved
		0x4000 4400 - 0x4000 47FF	USART1
		0x4000 4000 - 0x4000 43FF	Reserved
		0x4000 3C00 - 0x4000 3FFF	Reserved
		0x4000 3800 - 0x4000 3BFF	SPI1
		0x4000 3400 - 0x4000 37FF	Reserved
		0x4000 3000 - 0x4000 33FF	FWDGT
		0x4000 2C00 - 0x4000 2FFF	WWDGT
		0x4000 2800 - 0x4000 2BFF	RTC
		0x4000 2400 - 0x4000 27FF	Reserved
		0x4000 2000 - 0x4000 23FF	TIMER13
		0x4000 1400 - 0x4000 1FFF	Reserved
		0x4000 1000 - 0x4000 13FF	TIMER5
		0x4000 0800 - 0x4000 0FFF	Reserved
		0x4000 0400 - 0x4000 07FF	TIMER2
		0x4000 0000 - 0x4000 03FF	Reserved
SRAM		0x2000 2000 - 0x3FFF FFFF	Reserved
		0x2000 0000 - 0x2000 1FFF	SRAM
Code		0x1FFF F810 - 0x1FFF FFFF	Reserved
		0x1FFF F800 - 0x1FFF F80F	Option bytes
		0x1FFF EC00 - 0x1FFF F7FF	System memory
		0x0801 0000 - 0x1FFF EBFF	Reserved
		0x0800 0000 - 0x0800 FFFF	Main Flash memory
		0x0001 0000 - 0x07FF FFFF	Reserved

Pre-defined

Regions

Bus

ADDRESS

Peripherals

0x00000000 - 0x0000FFFF

Aliased to Flash or

system memory

GD32E230Cx LQFP48 pin definitions

Table 2-4. GD32E230Cx LQFP48 pin definitions

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VDD

Default: VDD

PC13- TAMPER-

RTC

I/O

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14-

OSC32IN

I/O

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

I/O

Default: PC15 Additional: OSC32OUT

PF0-OSCIN

I/O

5VT

Default: PF0 Alternate: I2C0_SDA

Additional: OSCIN

PF1- OSCOUT

I/O

5VT

Default: PF1

Alternate: I2C0_SCL Additional: OSCOUT

NRST

I/O

Default: NRST

VSSA

Default: VSSA

VDDA

Default: VDDA

PA0-WKUP

I/O

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5)

Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0

PA1

I/O

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5)

Additional: ADC_IN1, CMP_IP

PA2

I/O

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5)

Additional: ADC_IN2, CMP_IM7

PA3

I/O

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5)

Additional: ADC_IN3

PA4

I/O

Default: PA4

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Additional: ADC_IN4, CMP_IM4

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
				Default: PA5
PA5	15	I/O		Alternate: SPI0_SCK, I2S0_CK
				Additional: ADC_IN5, CMP_IM5
				Default: PA6
				Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
PA6	16	I/O		TIMER0_BRKIN, TIMER15_CH0, EVENTOUT,
				CMP_OUT
				Additional: ADC_IN6
				Default: PA7
				Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7	17	I/O		TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
				EVENTOUT
				Additional: ADC_IN7
				Default: PB0
PB0	18	I/O		Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT
				Additional: ADC_IN8
				Default: PB1
PB1	19	I/O		Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5)
				Additional: ADC_IN9
PB2	20	I/O	5VT	Default: PB2 Alternate: TIMER2_ETI
				Default: PB10
PB10	21	I/O	5VT	Alternate: I2C0_SCL(3),I2C1_SCL(5), SPI1_IO2(5),
				SPI1_SCK(5)
				Default: PB11
PB11	22	I/O	5VT	Alternate: I2C0_SDA(3),I2C1_SDA(5), EVENTOUT,
				SPI1_IO3(5)
VSS	23	P		Default: VSS
VDD	24	P		Default: VDD
				Default: PB12
PB12	25	I/O	5VT	Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BRKIN,
				I2C1_SMBA(5), EVENTOUT
				Default: PB13
PB13	26	I/O	5VT	Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON,
				I2C1_TXFRAME(5), I2C1_SCL(5)
				Default: PB14
PB14	27	I/O	5VT	Alternate: SPI0_MISO(3), SPI1_MISO(5),
				TIMER0_CH1_ON, TIMER14_CH0(5), I2C1_SDA(5)
				Default: PB15
				Alternate: SPI0_MOSI(3), SPI1_MOSI(5),
PB15	28	I/O	5VT	TIMER0_CH2_ON, TIMER14_CH0_ON(5),
				TIMER14_CH1(5)
				Additional: RTC_REFIN, WKUP6

Pin Name

Pins

Pin Type(1)

I/O Level(2)

Functions description

PA8

I/O

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT

PA9

I/O

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT

PA10

I/O

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2,

TIMER16_BRKIN, I2C0_SDA

PA11

I/O

5VT

Default: PA11

Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5)

PA12

I/O

5VT

Default: PA12

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5)

PA13

I/O

5VT

Default: PA13/SWDIO

Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5)

PF6

I/O

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

PF7

I/O

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

PA14

I/O

5VT

Default: PA14/SWCLK

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

PA15

I/O

5VT

Default: PA15

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT

PB3

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, I2S0_CK, EVENTOUT

PB4

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN

PB5

I/O

5VT

Default: PB5

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1

Additional: WKUP5

PB6

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

PB7

I/O

5VT

Default: PB7

Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON

BOOT0

Default: BOOT0

PB8

I/O

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

PB9

I/O

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
				EVENTOUT, I2S0_MCK, SPI1_NSS(5)
VSS	47	P		Default: VSS
VDD	48	P		Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32E230C4 devices only.
(4)Functions are available on GD32E230C8/6 devices.
(5)Functions are available on GD32E230C8 devices only.

GD32E230Kx LQFP32 pin definitions

Table 2-5. GD32E230Kx LQFP32 pin definitions

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VDD

Default: VDD

PF0-OSCIN

I/O

5VT

Default: PF0 Alternate: I2C0_SDA

Additional: OSCIN

PF1- OSCOUT

I/O

5VT

Default: PF1

Alternate: I2C0_SCL Additional: OSCOUT

NRST

I/O

Default: NRST

VDDA

Default: VDDA

PA0-WKUP

I/O

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5)

Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0

PA1

I/O

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5)

Additional: ADC_IN1, CMP_IP

PA2

I/O

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5)

Additional: ADC_IN2, CMP_IM7

PA3

I/O

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5)

Additional: ADC_IN3

PA4

I/O

Default: PA4

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
				Additional: ADC_IN4, CMP_IM4
				Default: PA5
PA5	11	I/O		Alternate: SPI0_SCK, I2S0_CK
				Additional: ADC_IN5, CMP_IM5
				Default: PA6
				Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
PA6	12	I/O		TIMER0_BRKIN, TIMER15_CH0, EVENTOUT,
				CMP_OUT
				Additional: ADC_IN6
				Default: PA7
				Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7	13	I/O		TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
				EVENTOUT
				Additional: ADC_IN7
				Default: PB0
PB0	14	I/O		Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT
				Additional: ADC_IN8
				Default: PB1
PB1	15	I/O		Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5)
				Additional: ADC_IN9
VSS	16	P		Default: VSS
VDD	17	P		Default: VDD
				Default: PA8
PA8	18	I/O	5VT	Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
				USART1_TX(4), EVENTOUT
				Default: PA9
PA9	19	I/O	5VT	Alternate: USART0_TX, TIMER0_CH1,
				TIMER14_BRKIN(5), I2C0_SCL, CK_OUT
				Default: PA10
PA10	20	I/O	5VT	Alternate: USART0_RX, TIMER0_CH2,
				TIMER16_BRKIN, I2C0_SDA
				Default: PA11
PA11	21	I/O	5VT	Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT,
				EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5)
				Default: PA12
PA12	22	I/O	5VT	Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,
				SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5)
PA13	23	I/O	5VT	Default: PA13/SWDIO Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5)
				Default: PA14/SWCLK
PA14	24	I/O	5VT	Alternate: USART0_TX(3), USART1_TX(4), SWCLK,
				SPI1_MOSI(5)
PA15	25	I/O	5VT	Default: PA15 Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

Pin Name

Pins

Pin Type(1)

I/O Level(2)

Functions description

USART1_RX(4), SPI1_NSS(5), EVENTOUT

PB3

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, I2S0_CK, EVENTOUT

PB4

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN

PB5

I/O

5VT

Default: PB5

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1

Additional: WKUP5

PB6

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

PB7

I/O

5VT

Default: PB7

Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON

BOOT0

Default: BOOT0

VSS

Default: VSS

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32E230K4 devices only.
(4)Functions are available on GD32E230K8/6 devices.
(5)Functions are available on GD32E230K8 devices only.

GD32E230Kx QFN32 pin definitions

Table 2-6. GD32E230Kx QFN32 pin definitions

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VDD

Default: VDD

PF0-OSCIN

I/O

5VT

Default: PF0 Alternate: I2C0_SDA

Additional: OSCIN

PF1- OSCOUT

I/O

5VT

Default: PF1 Alternate: I2C0_SCL

Additional: OSCOUT

NRST

I/O

Default: NRST

VDDA

Default: VDDA

PA0-WKUP

I/O

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5)

Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0

PA1

I/O

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5)

Pin Name

Pins

Pin Type(1)

I/O Level(2)

Functions description

Additional: ADC_IN1, CMP_IP

PA2

I/O

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5)

Additional: ADC_IN2, CMP_IM7

PA3

I/O

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5)

Additional: ADC_IN3

PA4

I/O

Default: PA4

Alternate: SPI0_NSS, I2S0_WS, USART0_CK⁽³⁾, USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Additional: ADC_IN4, CMP_IM4

PA5

I/O

Default: PA5

Alternate: SPI0_SCK, I2S0_CK Additional: ADC_IN5, CMP_IM5

PA6

I/O

Default: PA6

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, CMP_OUT

Additional: ADC_IN6

PA7

I/O

Default: PA7

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

Additional: ADC_IN7

PB0

I/O

Default: PB0

Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT

Additional: ADC_IN8

PB1

I/O

Default: PB1

Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5)

Additional: ADC_IN9

PB2

I/O

5VT

Default: PB2

Alternate: TIMER2_ETI

VDD

Default: VDD

PA8

I/O

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT

PA9

I/O

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT

PA10

I/O

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2,

TIMER16_BRKIN, I2C0_SDA

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PA11

I/O

5VT

Default: PA11

Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5)

PA12

I/O

5VT

Default: PA12

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5)

PA13

I/O

5VT

Default: PA13/SWDIO

Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5)

PA14

I/O

5VT

Default: PA14/SWCLK

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI⁽⁵⁾

PA15

I/O

5VT

Default: PA15

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT

PB3

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, I2S0_CK, EVENTOUT

PB4

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN

PB5

I/O

5VT

Default: PB5

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1

Additional: WKUP5

PB6

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

PB7

I/O

5VT

Default: PB7

Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON

BOOT0

Default: BOOT0

PB8

I/O

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

ARM® Cortex®-M23 core

The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M23 processor core
Up to 72 MHz operation frequency
Single-cycle multiplication and hardware divider
Ultra-low power, energy-efficient operation
Excellent code density
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M23 processor is based on the ARMv8-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M23:
Internal Bus Matrix connected with AHB master, Serial Wire Debug Port and Single-cycle IO port
Nested Vectored Interrupt Controller (NVIC)
Breakpoint Unit(BPU)
Data Watchpoint and Trace (DWT)
Serial Wire Debug Port

Embedded memory

Up to 64 Kbytes of Flash memory
Up to 8 Kbytes of SRAM with hardware parity checking

64 Kbytes of inner Flash and 8 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with 0~2 wait states. Table 2-3. GD32E230xx memory map shows the memory map of the GD32E230xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

3.3Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator

Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
1.8 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 72 MHz/72 MHz/72 MHz. See Figure 2-8. GD32E230xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.71 V and down to 1.67 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 1.8 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 1.8 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAK range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15 or PA2 and PA3).

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance

between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, CMP output, LVD output and USART wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA
Temperature sensor

One 12-bit 2 MSPS multi-channel ADC is integrated in the device. It has a total of 12 multiplexed channels: up to 10 external channels, 1 channel for internal temperature sensor (VSENSE) and 1 channel for internal reference voltage (VREFINT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timer (TIMER0) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

DMA

5 channels DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs and I2S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 39 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 39 general purpose I/O pins (GPIO) in GD32E230xx, named PA0 ~ PA15 and PB0 ~ PB15, PC13 ~ PC15, PF0 ~ PF1, PF6 ~ PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push- pull open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

One 16-bit advanced timer (TIMER0), up to five 16-bit general timers (TIMER2, TIMER13
~ TIMER16), and one 16-bit basic timer (TIMER5)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)

The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels.

It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER2 is based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload up counter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 can also be used as a simple 16-bit time base.

The GD32E230xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source

Real time clock (RTC)

Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.
Calendar with subsecond, second, minute, hour, week day, date, year and month automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy.

The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
Supports SAM_V mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to two SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Separate transmit and receive 32-bit FIFO with DMA capability (only in SPI1)
Data frame size can be 4 to 16 bits (only in SPI1)
Quad-SPI configuration available in master mode (only in SPI1)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Specially, SPI1 has separate transmit and receive 32- bit FIFO with DMA capability and its data frame size can be 4 to 16 bits. Quad-SPI master mode is also supported in SPI1.

Universal synchronous asynchronous receiver transmitter (USART)
Up to two USARTs with operating frequency up to 4.5 MBits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

One I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI0
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32E230xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI0. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.

Comparators (CMP)

One fast rail-to-rail low-power comparators with software configurable
Programmable reference voltage (internal or external I/O)

One Comparator (CMP) is implemented within the devices. It can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.

Debug mode

Serial wire debug port

Debug capabilities can be accessed by a debug tool via Serial Wire (SW - Debug Port).

Package and operation temperature

LQFP48 (GD32E230CxTx), LQFP32 (GD32E230KxTx), QFN32 (GD32E230KxUx), QFN28 (GD32E230GxUx), TSSOP20 (GD32E230FxPx) and LGA20 (GD32E230FxVx).
Operation temperature range: -40°C to +85°C (industrial level)

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uA級別智能門鎖低功耗雷達(dá)模塊讓門鎖更加智能省電節(jié)約功耗

 發(fā)布時(shí)間： : 2022-02--18

uA級別智能門鎖低功耗雷達(dá)模塊讓門鎖更加智能省電節(jié)約功耗，指紋門鎖并不是什么新鮮事，我相信每個人都很熟悉。隨著近年來智能家居的逐步普及，指紋門鎖也進(jìn)入了成千上萬的家庭。今天的功耗雷達(dá)模塊指紋門鎖不僅消除了繁瑣的鑰匙，而且還提供了各種智能功能，uA級別智能門鎖低功耗雷達(dá)模塊用在智能門鎖上，可以實(shí)現(xiàn)門鎖的智能感應(yīng)屏幕，使電池壽命延長3-5倍，如與其他智能家居連接，成為智能場景的開關(guān)。所以今天的指紋門鎖更被稱為智能門鎖。今天，讓我們來談?wù)劰睦走_(dá)模塊智能門鎖的安全性。希望能讓更多想知道智能門鎖的朋友認(rèn)識下。指紋識別是智能門鎖的核心指紋識別技術(shù)在我們的智能手機(jī)上隨處可見。從以前的實(shí)體指紋識別到屏幕下的指紋識別，可以說指紋識別技術(shù)已經(jīng)相當(dāng)成熟。指紋識別可以說是整個uA級低功耗雷達(dá)模塊智能門鎖的核心。目前主要有三種常見的指紋識別方法，即光學(xué)指紋識別、半導(dǎo)體指紋識別和超聲指紋識別。光學(xué)指紋識別讓我們先談?wù)劰鈱W(xué)指紋識別的原理實(shí)際上是光的反射。我們都知道指紋本身是不均勻的。當(dāng)光照射到我們的指紋上時(shí)，它會反射，光接收器可以通過接收反射的光來繪制我們的指紋。就像激光雷達(dá)測繪一樣。光學(xué)指紋識別通常出現(xiàn)在打卡機(jī)上，手機(jī)上的屏幕指紋識別技術(shù)也使用光學(xué)指紋識別。今天的光學(xué)指紋識別已經(jīng)達(dá)到了非?？斓淖R別速度。然而，光學(xué)指紋識別有一個缺點(diǎn)，即硬件上的活體識別無法實(shí)現(xiàn)，容易被指模破解。通常，活體識別是通過軟件算法進(jìn)行的。如果算法處理不當(dāng)，很容易翻車。此外，光學(xué)指紋識別也容易受到液體的影響，濕手解鎖的成功率也會下降。超聲指紋識別超聲指紋識別也被稱為射頻指紋識別，其原理與光學(xué)類型相似，但超聲波使用聲波反射，實(shí)際上是聲納的縮小版本。因?yàn)槭褂寐暡?，不要?dān)心水折射會降低識別率，所以超聲指紋識別可以濕手解鎖。然而，超聲指紋識別在防破解方面與光學(xué)類型一樣，不能實(shí)現(xiàn)硬件，可以被指模破解，活體識別仍然依賴于算法。半導(dǎo)體指紋識別半導(dǎo)體指紋識別主要采用電容、電場（即我們所說的電感）、溫度和壓力原理來實(shí)現(xiàn)指紋圖像的收集。當(dāng)用戶將手指放在前面時(shí)，皮膚形成電容陣列的極板，電容陣列的背面是絕緣極板。由于不同區(qū)域指紋的脊柱與谷物之間的距離也不同，因此每個單元的電容量隨之變化，從而獲得指紋圖像。半導(dǎo)體指紋識別具有價(jià)格低、體積小、識別率高的優(yōu)點(diǎn)，因此大多數(shù)uA級低功耗雷達(dá)模塊智能門鎖都采用了這種方案。半導(dǎo)體指紋識別的另一個功能是活體識別。傳統(tǒng)的硅膠指模無法破解。當(dāng)然，這并不意味著半導(dǎo)體可以百分識別活體。所謂的半導(dǎo)體指紋識別活體檢測不使用指紋活體體征。本質(zhì)上，它取決于皮膚的材料特性，這意味著雖然傳統(tǒng)的硅膠指模無法破解。一般來說，無論哪種指紋識別，都有可能被破解，只是說破解的水平。然而，今天的指紋識別，無論是硬件生活識別還是算法生活識別，都相對成熟，很難破解。畢竟，都可以通過支付級別的認(rèn)證，大大保證安全。目前，市場上大多數(shù)智能門鎖仍將保留鑰匙孔。除了指紋解鎖外，用戶還可以用傳統(tǒng)鑰匙開門。留下鑰匙孔的主要目的是在指紋識別故障或智能門鎖耗盡時(shí)仍有開門的方法。但由于有鑰匙孔，它表明它可以通過技術(shù)手段解鎖。目前市場上的鎖等級可分為A、B、C三個等級，這三個等級主要是通過防暴開鎖和防技術(shù)開鎖的程度來區(qū)分的。A級鎖要求技術(shù)解鎖時(shí)間不少于1分鐘，B級鎖要求不少于5分鐘。即使是高級別的C級鎖也只要求技術(shù)解鎖時(shí)間不少于10分鐘。也就是說，現(xiàn)在市場上大多數(shù)門鎖，無論是什么級別，在專業(yè)的解鎖大師面前都糊，只不過是時(shí)間長短。安全是重要的，是否安全增加了人們對uA級別低功耗雷達(dá)模塊智能門鎖安全的擔(dān)憂。事實(shí)上，現(xiàn)在到處都是攝像頭，強(qiáng)大的人臉識別，以及移動支付的出現(xiàn)，使家庭現(xiàn)金減少，所有這些都使得入室盜竊的成本急劇上升，近年來各省市的入室盜竊幾乎呈懸崖狀下降。換句話說，無論鎖有多安全，無論鎖有多難打開，都可能比在門口安裝攝像頭更具威懾力。因此，擔(dān)心uA級別低功耗雷達(dá)模塊智能門鎖是否不安全可能意義不大。畢竟，家里的防盜鎖可能不安全。我們應(yīng)該更加關(guān)注門鎖能給我們帶來多少便利。我們要考慮的是智能門鎖的兼容性和通用性。畢竟，智能門鎖近年來才流行起來。大多數(shù)人在后期將普通機(jī)械門鎖升級為智能門鎖。因此，智能門鎖能否與原門兼容是非常重要的。如果不兼容，發(fā)現(xiàn)無法安裝是一件非常麻煩的事情。 uA級別低功耗雷達(dá)模塊智能門鎖主要是為了避免帶鑰匙的麻煩。因此，智能門鎖的便利性尤為重要。便利性主要體現(xiàn)在指紋的識別率上。手指受傷導(dǎo)致指紋磨損或老年人指紋較淺。智能門鎖能否識別是非常重要的。當(dāng)然，如果指紋真的失效，是否有其他解鎖方案，如密碼解鎖或NFC解鎖。還需要注意密碼解鎖是否有虛假密碼等防窺鏡措施。當(dāng)然，智能門鎖的耐久性也是一個需要特別注意的地方。uA級別低功耗雷達(dá)模塊智能門鎖主要依靠內(nèi)部電池供電，這就要求智能門鎖的耐久性盡可能好，否則經(jīng)常充電或更換電池會非常麻煩。智能門鎖低功耗雷達(dá)模塊：讓門鎖更加智能省電節(jié)約功耗在當(dāng)今信息化時(shí)代，智能門鎖已經(jīng)成為人們生活中不可或缺的一部分。對于門鎖制造商來說，如何提高門鎖的安全性、實(shí)用性和便利性，成為他們面對的重要課題。隨著人們對門鎖智能化的需求越來越高，門鎖的能耗問題也成為了門鎖制造商需要重視的問題。為此，越來越多的門鎖制造商開始推出以低功耗為主題的系列產(chǎn)品。在這樣的背景下，智能門鎖低功耗雷達(dá)模塊應(yīng)運(yùn)而生。智能門鎖低功耗雷達(dá)模塊是一種新型技術(shù)，其采取雷達(dá)技術(shù)對門鎖周圍的物體進(jìn)行探測，一旦發(fā)現(xiàn)門鎖附近有人靠近，便會將門鎖自動解鎖，無需使用鑰匙。同時(shí)，在保持智能控制的前提下，實(shí)現(xiàn)了門鎖省電、節(jié)約功耗，延長門鎖使用壽命。在使用智能門鎖低功耗雷達(dá)模塊的門鎖中，控制電路和自動解鎖機(jī)制是關(guān)鍵的部件?？刂齐娐凡捎孟冗M(jìn)的芯片技術(shù)，通過優(yōu)秀的功耗控制以實(shí)現(xiàn)模塊化管理。而自動解鎖機(jī)制不僅可以通過微波信號控制實(shí)現(xiàn)門鎖的無鑰匙解鎖，還能夠在門鎖未處理的情況下自動鎖定，保障門鎖的安全。智能門鎖低功耗雷達(dá)模塊的主要特點(diǎn)是：低功耗、高靈敏度和高可靠性。該模塊在進(jìn)行人體檢測時(shí)，可以遠(yuǎn)距離探測到距離為5-7米遠(yuǎn)處的人體信號，目標(biāo)檢測速度極快，而且對門鎖周圍的環(huán)境要求不高。同時(shí)，該模塊采用了自適應(yīng)自動補(bǔ)償技術(shù)，能夠根據(jù)不同環(huán)境的變化自動調(diào)整信號發(fā)射和接收參數(shù)，減小誤檢率。在使用智能門鎖低功耗雷達(dá)模塊的門鎖中，其功耗可以做到非常低，一組電池能夠支持門鎖持續(xù)使用幾年左右。而且這樣的智能門鎖除了具有自動解鎖的功能，還可與APP相互匹配，實(shí)現(xiàn)了遠(yuǎn)程操作的便捷性。總的來說，智能門鎖低功耗雷達(dá)模塊的問世，解決了門鎖安全性和省電節(jié)省方面的問題，是智能門鎖材料不可或缺的一部分。作為門鎖制造商，只有不斷創(chuàng)新，利用這種新型技術(shù)，將會在行業(yè)中占據(jù)重要的地位。除了上文所述的主要特點(diǎn)和優(yōu)勢，智能門鎖低功耗雷達(dá)模塊還具有以下幾點(diǎn)： 1. 實(shí)時(shí)監(jiān)測門鎖周圍環(huán)境變化，通過物體的距離體積和運(yùn)動來確定是否有人靠近門鎖，并控制門鎖的開啟或關(guān)閉，使得門鎖更加智能化。 2. 可對門鎖附件進(jìn)行檢測，如門掛、門應(yīng)急照明燈以及緊急呼叫按鈕等，并及時(shí)給出響應(yīng)，確保門鎖能夠正常運(yùn)作。這樣，門鎖在不受干擾的情況下，能夠保持安全通道。 3. 通過智能學(xué)習(xí)技術(shù)，能夠自適應(yīng)網(wǎng)站多種環(huán)境的變化，讓智能門鎖低功耗雷達(dá)模塊更加準(zhǔn)確和精細(xì)的控制門鎖的開關(guān)，節(jié)約能耗并延長使用壽命。 4. 能夠與其他智能電器相連，如智能家居系統(tǒng)、電視等，形成智能家居生態(tài)圈，更好地控制家庭訪客進(jìn)出，讓生活更加方便。綜上所述，智能門鎖低功耗雷達(dá)模塊的出現(xiàn)，對提升門鎖能耗管理和智能化有著重要作用。門鎖制造商只有將這些新型技術(shù)運(yùn)用到門鎖產(chǎn)品中，才能更加貼合用戶需求，滿足消費(fèi)市場的日益增長的智能化需求。

2022-01

微波雷達(dá)傳感器雷達(dá)感應(yīng)浴室鏡上的應(yīng)用

 發(fā)布時(shí)間： : 2022-01--14

微波雷達(dá)傳感器雷達(dá)感應(yīng)浴室鏡上的應(yīng)用，如今，家用電器的智能化已成為一種常態(tài)，越來越多的人開始在自己的浴室里安裝智能浴室鏡。但是還有很多人對智能浴鏡的理解還不夠深入，今天就來說說這個話題。什么是智能浴室鏡？智慧型浴室鏡，顧名思義，就是衛(wèi)浴鏡子智能化升級，入門級產(chǎn)品基本具備了彩燈和鏡面觸摸功能，更高檔次的產(chǎn)品安裝有微波雷達(dá)傳感器智能感應(yīng)，當(dāng)感應(yīng)到有人接近到一定距離即可開啟亮燈或者亮屏操作，也可三色無極調(diào)，智能除霧，語音交互，日程安排備忘，甚至在鏡子上看電視，聽音樂，氣象預(yù)報(bào)，問題查詢，智能控制，健康管理等。智能化雷達(dá)感應(yīng)浴室鏡與普通鏡的區(qū)別，為什么要選TA？，就功能而言，普通浴鏡價(jià)格用它沒有什么壓力！而且雷達(dá)感應(yīng)智能浴鏡會讓人猶豫不決是否“值得一看”。就功能和應(yīng)用而言，普通浴鏡功能單一，而微波雷達(dá)傳感器智能浴室鏡功能創(chuàng)新：鏡子燈光色溫和亮度可以自由調(diào)節(jié)，鏡面還可以濕手觸控，智能除霧，既環(huán)保又健康！盡管智能浴鏡比較新穎，但功能豐富，體驗(yàn)感更好，特別是入門級的智能浴鏡，具有基礎(chǔ)智能化功能，真的適合想體驗(yàn)下智能化的小伙伴們。給衛(wèi)生間安裝微波雷達(dá)傳感器浴室鏡安裝注意什么？ ①確定智能浴室鏡的安裝位置，因?yàn)槭前惭b時(shí)在墻壁上打孔，一旦安裝后一般無法移動位置。 ②在選購雷達(dá)感應(yīng)智能浴室鏡時(shí)，根據(jù)安裝位置確定鏡子的形狀和尺寸。 ③確定智能浴鏡的安裝位置后，在布線時(shí)為鏡子預(yù)留好電源線。 ④確定微波雷達(dá)傳感器智能浴鏡的安裝高度，一般智能浴鏡的標(biāo)準(zhǔn)安裝高度約85cm(從地磚到鏡子底)，具體安裝高度要根據(jù)家庭成員的身高及使用習(xí)慣來決定。 ⑤鏡面遇到污漬，可用酒精或30%清潔稀釋液擦洗，平時(shí)可用干毛巾養(yǎng)護(hù)，注意多通風(fēng)。

2024-10

安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊的接線方式詳解

 發(fā)布時(shí)間： : 2024-10--18

在安防監(jiān)控領(lǐng)域，球機(jī)雷達(dá)開關(guān)模塊是保障監(jiān)控系統(tǒng)穩(wěn)定運(yùn)行的關(guān)鍵組件之一。其接線方式的正確與否直接關(guān)系到監(jiān)控系統(tǒng)的整體性能和安全性。本文將圍繞安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊的接線方式展開，詳細(xì)介紹其接線步驟、注意事項(xiàng)以及常見問題解決方案，旨在幫助讀者更好地理解和應(yīng)用這一技術(shù)。一、引言隨著科技的不斷發(fā)展，安防監(jiān)控系統(tǒng)在各個領(lǐng)域的應(yīng)用越來越廣泛。球機(jī)雷達(dá)開關(guān)模塊作為監(jiān)控系統(tǒng)的重要組成部分，其性能的穩(wěn)定性和可靠性對于整個系統(tǒng)的運(yùn)行至關(guān)重要。因此，掌握正確的接線方式對于保障監(jiān)控系統(tǒng)的正常運(yùn)行具有重要意義。二、安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊概述安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊是一種集成了雷達(dá)探測和開關(guān)控制功能的智能設(shè)備。它通過雷達(dá)技術(shù)實(shí)時(shí)監(jiān)測監(jiān)控區(qū)域的動態(tài)情況，并根據(jù)需要控制球機(jī)的旋轉(zhuǎn)和鏡頭變焦，實(shí)現(xiàn)對監(jiān)控區(qū)域的全方位、無死角的監(jiān)控。該模塊具有響應(yīng)速度快、準(zhǔn)確性高、穩(wěn)定性好等優(yōu)點(diǎn)，在安防監(jiān)控領(lǐng)域得到了廣泛應(yīng)用。三、安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊的接線方式（一）接線前準(zhǔn)備在進(jìn)行安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊的接線前，需要做好以下準(zhǔn)備工作：檢查設(shè)備是否完好無損，確保所有部件齊全、無損壞。準(zhǔn)備所需的工具，如螺絲刀、剝線鉗、絕緣膠帶等。確認(rèn)電源線和信號線的規(guī)格和數(shù)量，確保與設(shè)備要求相匹配。（二）接線步驟連接電源線首先，將電源線的火線（通常為紅色）連接到雷達(dá)開關(guān)模塊的電源正（通常為“+”或“VCC”標(biāo)識），將電源線的零線（通常為黑色或藍(lán)色）連接到雷達(dá)開關(guān)模塊的電源負(fù)（通常為“-”或“GND”標(biāo)識）。注意，在接線過程中要確保電源線的正負(fù)與設(shè)備要求相匹配，避免出現(xiàn)接反或短路的情況。連接信號線信號線主要用于傳輸雷達(dá)探測信號和控制信號。在連接信號線時(shí)，需要將雷達(dá)開關(guān)模塊的信號輸出端口與球機(jī)的信號輸入端口相連接。具體接線方式可能因設(shè)備型號而異，但一般來說，需要將信號線的正（通常為紅色）連接到雷達(dá)開關(guān)模塊的信號輸出正（通常為“S+”或“OUT+”標(biāo)識），將信號線的負(fù)（通常為黑色或藍(lán)色）連接到雷達(dá)開關(guān)模塊的信號輸出負(fù)（通常為“S-”或“OUT-”標(biāo)識）。同樣地，在接線過程中要確保信號線的正負(fù)與設(shè)備要求相匹配，避免出現(xiàn)接反或短路的情況。檢查接線在完成電源線和信號線的連接后，需要仔細(xì)檢查所有接線是否牢固、無松動或裸露部分。同時(shí)，還需要檢查所有接線是否正確無誤，避免出現(xiàn)接錯或漏接的情況。（三）注意事項(xiàng) 在進(jìn)行接線前，務(wù)必確保設(shè)備已經(jīng)關(guān)閉并斷開電源，以避免因操作不當(dāng)而導(dǎo)致設(shè)備損壞或人身傷害。在選擇電源線和信號線時(shí)，要確保其規(guī)格和數(shù)量與設(shè)備要求相匹配，避免出現(xiàn)電壓過高或電流過大等安全隱患。在連接信號線時(shí)，要特別注意信號線的正負(fù)與設(shè)備要求相匹配，避免出現(xiàn)接反或短路的情況。在檢查接線時(shí)，要仔細(xì)檢查所有接線是否牢固、無松動或裸露部分，以確保設(shè)備的安全運(yùn)行。四、常見問題及解決方案（一）雷達(dá)開關(guān)模塊無法正常工作可能原因：電源線接反或短路。信號線接反或短路。設(shè)備本身故障。解決方案：檢查電源線和信號線的連接是否正確無誤，確保正負(fù)與設(shè)備要求相匹配。檢查電源線和信號線是否牢固、無松動或裸露部分。如果以上檢查均正常，但雷達(dá)開關(guān)模塊仍無法正常工作，可能是設(shè)備本身故障，需要聯(lián)系廠家或?qū)I(yè)維修人員進(jìn)行維修或更換。（二）球機(jī)無法響應(yīng)雷達(dá)開關(guān)模塊的控制信號可能原因：信號線連接錯誤或松動。球機(jī)本身故障。解決方案：檢查信號線的連接是否正確無誤，確保正負(fù)與設(shè)備要求相匹配，并且信號線牢固、無松動或裸露部分。如果信號線連接正常但球機(jī)仍無法響應(yīng)控制信號，可能是球機(jī)本身故障，需要聯(lián)系廠家或?qū)I(yè)維修人員進(jìn)行維修或更換。五、總結(jié) 本文詳細(xì)介紹了安防監(jiān)控球機(jī)雷達(dá)開關(guān)模塊的接線方式及注意事項(xiàng)，并針對常見問題提供了解決方案。通過掌握正確的接線方式和注意事項(xiàng)，讀者可以更好地應(yīng)用這一技術(shù)，提高監(jiān)控系統(tǒng)的性能和安全性。

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