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兆易創(chuàng)新GD32-GigaDevice-兆易創(chuàng)新代理

兆易創(chuàng)新GD32E103CBT6-GD32 ARM Cortex-M4 Microcontroller

兆易創(chuàng)新GD32E103CBT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32E103xx ARM? Cortex?-M4 32-bit MCU Datasheet General description The GD32E103xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM? Cortex?-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex?-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides powerful trace technology for enhanced application security and advanced debug support. The GD32E103xx device incorporates the ARM? Cortex?-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and 32 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 3 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss, an USBFS and two CANs. The device operates from 1.71 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make GD32E103xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, motor drives, consumer and handheld equipment, human machine interface, security and alarm systems, POS, automotive navigation, IoT and so on. Device information Table 2-1. GD32E103xx devices features and peripheral list ? Part Number GD32E103xx ? T8 TB C8 CB R8 RB V8 VB Flash (KB) 64 128 64 128 64 128 64 128 SRAM (KB) 20 32 20 32 20 32 20 32 Timers General timer(16- bit) 4 (1-4) 4 (1-4) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) ? Advanced timer(16-bit) 1 (0) 1 (0) 1 (0) 1 (0) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) ? SysTick 1 1 1 1 1 1 1 1 ? ? Basic timer(16-bit) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) ? Watchdog 2 2 2 2 2 2 2 2 ? RTC 1 1 1 1 1 1 1 1 Connectivity ? USART 2 (0-1) 2 (0-1) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) ? ? UART 0 0 0 0 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) ? ? I2C 1 (0) 1 (0) 2 (0-1) 2 (0-1) 2 (0-1) 2 (0-1) 2 (0-1) 2 (0-1) ? ? SPI/I2S 1/0 (0/-) 1/0 (0/-) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) ? CAN 2xFD 2xFD 2xFD 2xFD 2xFD 2xFD 2xFD 2xFD ? USBFS 1 1 1 1 1 1 1 1 GPIO 26 26 37 37

產(chǎn)品描述

GigaDevice Semiconductor Inc.
GD32E103xx
ARM® Cortex™-M4 32-bit MCU
Datasheet

General description

The GD32E103xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex™-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides powerful trace technology for enhanced application security and advanced debug support.
The GD32E103xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and 32 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 3 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss, an USBFS and two CANs.
The device operates from 1.71 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make GD32E103xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, motor drives, consumer and handheld equipment, human machine interface, security and alarm systems, POS, automotive navigation, IoT and so on.

Device information

Table 2-1. GD32E103xx devices features and peripheral list

Part Number		GD32E103xx
		T8	TB	C8	CB	R8	RB	V8	VB
Flash (KB)		64	128	64	128	64	128	64	128
SRAM (KB)		20	32	20	32	20	32	20	32
Timers	General timer(16- bit)	4 (1-4)	4 (1-4)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)
	Advanced timer(16-bit)	1 (0)	1 (0)	1 (0)	1 (0)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)
	SysTick	1	1	1	1	1	1	1	1
	Basic timer(16-bit)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)
	Watchdog	2	2	2	2	2	2	2	2
	RTC	1	1	1	1	1	1	1	1
Connectivity	USART	2 (0-1)	2 (0-1)	3 (0-2)	3 (0-2)	3 (0-2)	3 (0-2)	3 (0-2)	3 (0-2)
	UART	0	0	0	0	2 (3-4)	2 (3-4)	2 (3-4)	2 (3-4)
	I2C	1 (0)	1 (0)	2 (0-1)	2 (0-1)	2 (0-1)	2 (0-1)	2 (0-1)	2 (0-1)
	SPI/I2S	1/0 (0/-)	1/0 (0/-)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)
	CAN	2xFD	2xFD	2xFD	2xFD	2xFD	2xFD	2xFD	2xFD
	USBFS	1	1	1	1	1	1	1	1
GPIO		26	26	37	37	51	51	80	80
EXMC		0	0	0	0	0	0	1	1
EXTI		16	16	16	16	16	16	16	16
ADC	Units	2	2	2	2	2	2	2	2
	Channels	10	10	10	10	16	16	16	16
DAC		2	2	2	2	2	2	2	2
Package		QFN36		LQFP48		LQFP64		LQFP100

Memory map

Table 2-2. GD32E103xx memory map

Pre-defined regions	Bus	Address	Peripherals
External device	AHB3	0xA000 0000 - 0xA000 0FFF	EXMC - SWREG
External RAM		0x9000 0000 - 0x9FFF FFFF	Reserved
		0x7000 0000 - 0x8FFF FFFF	Reserved
		0x6000 0000 - 0x63FF FFFF	EXMC - NOR/PSRAM/SRAM
Peripheral	AHB1	0x5000 0000 - 0x5003 FFFF	USBFS
		0x4008 0000 - 0x4FFF FFFF	Reserved
		0x4004 0000 - 0x4007 FFFF	Reserved
		0x4002 BC00 - 0x4003 FFFF	Reserved
		0x4002 B000 - 0x4002 BBFF	Reserved
		0x4002 A000 - 0x4002 AFFF	Reserved
		0x4002 8000 - 0x4002 9FFF	Reserved
		0x4002 6800 - 0x4002 7FFF	Reserved
		0x4002 6400 - 0x4002 67FF	Reserved
		0x4002 6000 - 0x4002 63FF	Reserved
		0x4002 5000 - 0x4002 5FFF	Reserved
		0x4002 4000 - 0x4002 4FFF	Reserved
		0x4002 3C00 - 0x4002 3FFF	Reserved

Pre-defined regions	Bus	Address
		0x4002 3800 - 0x4002 3BFF
		0x4002 3400 - 0x4002 37FF
		0x4002 3000 - 0x4002 33FF
		0x4002 2C00 - 0x4002 2FFF
		0x4002 2800 - 0x4002 2BFF
		0x4002 2400 - 0x4002 27FF
		0x4002 2000 - 0x4002 23FF
		0x4002 1C00 - 0x4002 1FFF
		0x4002 1800 - 0x4002 1BFF
		0x4002 1400 - 0x4002 17FF
		0x4002 1000 - 0x4002 13FF
		0x4002 0C00 - 0x4002 0FFF
		0x4002 0800 - 0x4002 0BFF
		0x4002 0400 - 0x4002 07FF
		0x4002 0000 - 0x4002 03FF
		0x4001 8400 - 0x4001 FFFF
		0x4001 8000 - 0x4001 83FF
	APB2	0x4001 7C00 - 0x4001 7FFF
		0x4001 7800 - 0x4001 7BFF
		0x4001 7400 - 0x4001 77FF
		0x4001 7000 - 0x4001 73FF
		0x4001 6C00 - 0x4001 6FFF
		0x4001 6800 - 0x4001 6BFF
		0x4001 5C00 - 0x4001 67FF
		0x4001 5800 - 0x4001 5BFF
		0x4001 5400 - 0x4001 57FF
		0x4001 5000 - 0x4001 53FF
		0x4001 4C00 - 0x4001 4FFF
		0x4001 4800 - 0x4001 4BFF
		0x4001 4400 - 0x4001 47FF
		0x4001 4000 - 0x4001 43FF
		0x4001 3C00 - 0x4001 3FFF
		0x4001 3800 - 0x4001 3BFF
		0x4001 3400 - 0x4001 37FF
		0x4001 3000 - 0x4001 33FF
		0x4001 2C00 - 0x4001 2FFF
		0x4001 2800 - 0x4001 2BFF
		0x4001 2400 - 0x4001 27FF
		0x4001 2000 - 0x4001 23FF

Pre-defined regions	Bus	Address	Peripherals
		0x4001 1C00 - 0x4001 1FFF	Reserved
		0x4001 1800 - 0x4001 1BFF	GPIOE
		0x4001 1400 - 0x4001 17FF	GPIOD
		0x4001 1000 - 0x4001 13FF	GPIOC
		0x4001 0C00 - 0x4001 0FFF	GPIOB
		0x4001 0800 - 0x4001 0BFF	GPIOA
		0x4001 0400 - 0x4001 07FF	EXTI
		0x4001 0000 - 0x4001 03FF	AFIO
	APB1	0x4000 CC00 - 0x4000 FFFF	Reserved
		0x4000 C800 - 0x4000 CBFF	CTC
		0x4000 C400 - 0x4000 C7FF	Reserved
		0x4000 C000 - 0x4000 C3FF	Reserved
		0x4000 8000 - 0x4000 BFFF	Reserved
		0x4000 7C00 - 0x4000 7FFF	Reserved
		0x4000 7800 - 0x4000 7BFF	Reserved
		0x4000 7400 - 0x4000 77FF	DAC
		0x4000 7000 - 0x4000 73FF	PMU
		0x4000 6C00 - 0x4000 6FFF	BKP
		0x4000 6800 - 0x4000 6BFF	CAN1
		0x4000 6400 - 0x4000 67FF	CAN0
		0x4000 6000 - 0x4000 63FF	CAN SRAM 1K bytes
		0x4000 5C00 - 0x4000 5FFF	Reserved
		0x4000 5800 - 0x4000 5BFF	I2C1
		0x4000 5400 - 0x4000 57FF	I2C0
		0x4000 5000 - 0x4000 53FF	UART4
		0x4000 4C00 - 0x4000 4FFF	UART3
		0x4000 4800 - 0x4000 4BFF	USART2
		0x4000 4400 - 0x4000 47FF	USART1
		0x4000 4000 - 0x4000 43FF	Reserved
		0x4000 3C00 - 0x4000 3FFF	SPI2/I2S2
		0x4000 3800 - 0x4000 3BFF	SPI1/I2S1
		0x4000 3400 - 0x4000 37FF	Reserved
		0x4000 3000 - 0x4000 33FF	FWDGT
		0x4000 2C00 - 0x4000 2FFF	WWDGT
		0x4000 2800 - 0x4000 2BFF	RTC
		0x4000 2400 - 0x4000 27FF	Reserved
		0x4000 2000 - 0x4000 23FF	TIMER13
		0x4000 1C00 - 0x4000 1FFF	TIMER12
		0x4000 1800 - 0x4000 1BFF	TIMER11

Pre-defined regions	Bus	Address	Peripherals
		0x4000 1400 - 0x4000 17FF	TIMER6
		0x4000 1000 - 0x4000 13FF	TIMER5
		0x4000 0C00 - 0x4000 0FFF	TIMER4
		0x4000 0800 - 0x4000 0BFF	TIMER3
		0x4000 0400 - 0x4000 07FF	TIMER2
		0x4000 0000 - 0x4000 03FF	TIMER1
SRAM	AHB	0x2007 0000 - 0x3FFF FFFF	Reserved
		0x2006 0000 - 0x2006 FFFF	Reserved
		0x2003 0000 - 0x2005 FFFF	Reserved
		0x2002 0000 - 0x2002 FFFF	Reserved
		0x2001 C000 - 0x2001 FFFF	SRAM
		0x2001 8000 - 0x2001 BFFF
		0x2000 5000 - 0x2001 7FFF
		0x2000 0000 - 0x2000 4FFF
Code	AHB	0x1FFF F810 - 0x1FFF FFFF	Reserved
		0x1FFF F800 - 0x1FFF F80F	Option Bytes
		0x1FFF F000 - 0x1FFF F7FF	Boot loader
		0x1FFF C010 - 0x1FFF EFFF
		0x1FFF C000 - 0x1FFF C00F
		0x1FFF B000 - 0x1FFF BFFF
		0x1FFF 7A10 - 0x1FFF AFFF	Reserved
		0x1FFF 7800 - 0x1FFF 7A0F	Reserved
		0x1FFF 0000 - 0x1FFF 77FF	Reserved
		0x1FFE C010 - 0x1FFE FFFF	Reserved
		0x1FFE C000 - 0x1FFE C00F	Reserved
		0x1001 0000 - 0x1FFE BFFF	Reserved
		0x1000 0000 - 0x1000 FFFF	Reserved
		0x083C 0000 - 0x0FFF FFFF	Reserved
		0x0830 0000 - 0x083B FFFF	Reserved
		0x0810 0000 - 0x082F FFFF	Main Flash
		0x0802 0000 - 0x080F FFFF
		0x0800 0000 - 0x0801 FFFF
		0x0030 0000 - 0x07FF FFFF	Reserved
		0x0010 0000 - 0x002F FFFF	Aliased to Main Flash or Boot loader
		0x0002 0000 - 0x000F FFFF
		0x0000 0000 - 0x0001 FFFF

GD32E103Vx LQFP100 pin definitions

Table 2-3. GD32E103Vx LQFP100 pin definitions

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PE2

I/O

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

PE3

I/O

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

PE4

I/O

5VT

Default: PE4

Alternate: TRACED1, EXMC_A20

PE5

I/O

5VT

Default: PE5

Alternate: TRACED2, EXMC_A21 Remap: TIMER8_CH0

PE6

I/O

5VT

Default: PE6

Alternate: TRACED3, EXMC_A22 Remap: TIMER8_CH1

VBAT

Default: VBAT

PC13- TAMPER-

RTC

I/O

Default: PC13

Alternate: RTC_TAMPER

PC14-

OSC32IN

I/O

Default: PC14

Alternate: OSC32IN

PC15- OSC32OU

I/O

Default: PC15 Alternate: OSC32OUT

VSS_5

Default: VSS_5

VDD_5

Default: VDD_5

OSCIN

Default: OSCIN

Remap: PD0

OSCOUT

Default: OSCOUT

Remap:PD1

NRST

I/O

Default: NRST

PC0

I/O

Default: PC0

Alternate: ADC01_IN10

PC1

I/O

Default: PC1

Alternate: ADC01_IN11

PC2

I/O

Default: PC2

Alternate: ADC01_IN12

PC3

I/O

Default: PC3

Alternate: ADC01_IN13

VSSA

Default: VSSA

VREF-

Default: VREF-

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VREF+

Default: VREF+

VDDA

Default: VDDA

PA0-WKUP

I/O

Default: PA0

Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0_ETI, TIMER4_CH0, TIMER7_ETI

PA1

I/O

Default: PA1

Alternate: USART1_RTS, ADC01_IN1, TIMER4_CH1, TIMER1_CH1

PA2

I/O

Default: PA2

Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER8_CH0, TIMER1_CH2, SPI0_IO2

PA3

I/O

Default: PA3

Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, TIMER8_CH1, SPI0_IO3

VSS_4

Default: VSS_4

VDD_4

Default: VDD_4

PA4

I/O

Default: PA4

Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4

Remap: SPI2_NSS, I2S2_WS

PA5

I/O

Default: PA5

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

PA6

I/O

Default: PA6

Alternate: SPI0_MISO, TIMER7_BKIN, ADC01_IN6, TIMER2_CH0, TIMER12_CH0

Remap: TIMER0_BKIN

PA7

I/O

Default: PA7

Alternate: SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7, TIMER2_CH1, TIMER13_CH0

Remap: TIMER0_CH0_ON

PC4

I/O

Default: PC4

Alternate: ADC01_IN14

PC5

I/O

Default: PC5

Alternate: ADC01_IN15

PB0

I/O

Default: PB0

Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON

Remap: TIMER0_CH1_ON

PB1

I/O

Default: PB1

Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON

Remap: TIMER0_CH2_ON

PB2

I/O

5VT

Default: PB2, BOOT1

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PE7

I/O

5VT

Default: PE7 Alternate: EXMC_D4

Remap: TIMER0_ETI

PE8

I/O

5VT

Default: PE8 Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

PE9

I/O

5VT

Default: PE9 Alternate: EXMC_D6

Remap: TIMER0_CH0

PE10

I/O

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

PE11

I/O

5VT

Default: PE11

Alternate: EXMC_D8 Remap: TIMER0_CH1

PE12

I/O

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

PE13

I/O

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2

PE14

I/O

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3

PE15

I/O

5VT

Default: PE15 Alternate: EXMC_D12

Remap: TIMER0_BKIN

PB10

I/O

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2

PB11

I/O

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3

VSS_1

Default: VSS_1

VDD_1

Default: VDD_1

PB12

I/O

5VT

Default: PB12

Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, CAN1_RX

PB13

I/O

5VT

Default: PB13

Alternate: SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, CAN1_TX, I2C1_TXFRAME

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PB14

I/O

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0

PB15

I/O

5VT

Default: PB15

Alternate: SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON, TIMER11_CH11

PD8

I/O

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX

PD9

I/O

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX

PD10

I/O

5VT

Default: PD10

Alternate: EXMC_D15 Remap: USART2_CK

PD11

I/O

5VT

Default: PD11 Alternate: EXMC_A16

Remap: USART2_CTS

PD12

I/O

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS

PD13

I/O

5VT

Default: PD13 Alternate: EXMC_A18

Remap: TIMER3_CH1

PD14

I/O

5VT

Default: PD14 Alternate: EXMC_D0

Remap: TIMER3_CH2

PD15

I/O

5VT

Default: PD15 Alternate: EXMC_D1

Remap: TIMER3_CH3, CTC_SYNC

PC6

I/O

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

PC7

I/O

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

PC8

I/O

5VT

Default: PC8

Alternate: TIMER7_CH2 Remap: TIMER2_CH2

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PC9

I/O

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

PA8

I/O

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC

PA9

I/O

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

PA10

I/O

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, V1REF

PA11

I/O

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

PA12

I/O

5VT

Default: PA12

Alternate: USART0_RTS, CAN0_TX, USBFS_DP, TIMER0_ETI

PA13

I/O

5VT

Default: JTMS, SWDIO

Remap: PA13

VSS_2

Default: VSS_2

VDD_2

Default: VDD_2

PA14

I/O

5VT

Default: JTCK, SWCLK

Remap:PA14

PA15

I/O

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

PC10

I/O

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

PC11

I/O

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

PC12

I/O

5VT

Default: PC12 Alternate: UART4_TX

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

PD0

I/O

5VT

Default: PD0 Alternate: EXMC_D2

Remap: OSCIN, CAN0_RX

PD1

I/O

5VT

Default: PD1 Alternate: EXMC_D3

Remap: OSCOUT, CAN0_TX

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PD2

I/O

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

PD3

I/O

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS

PD4

I/O

5VT

Default: PD4

Alternate: EXMC_NOE Remap: USART1_RTS

PD5

I/O

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

PD6

I/O

5VT

Default: PD6

Alternate: EXMC_NWAIT Remap: USART1_RX

PD7

I/O

5VT

Default: PD7 Alternate: EXMC_NE0

Remap: USART1_CK

PB3

I/O

5VT

Default: JTDO

Alternate: SPI2_SCK, I2S2_CK

Remap: TIMER1_CH1, PB3, TRACESWO, SPI0_SCK

PB4

I/O

5VT

Default: NJTRST

Alternate: SPI2_MISO, I2C0_TXFRAME Remap: TIMER2_CH0, PB4, SPI0_MISO

PB5

I/O

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

PB6

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX, SPI0_IO2

PB7

I/O

5VT

Default: PB7

Alternate: I2C0_SDA, TIMER3_CH1, EXMC_NL(NADV) Remap: USART0_RX, SPI0_IO3

BOOT0

Default: BOOT0

PB8

I/O

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0 Remap: I2C0_SCL, CAN0_RX

PB9

I/O

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0 Remap: I2C0_SDA, CAN0_TX

PE0

I/O

5VT

Default:PE0

Alternate: TIMER3_ETI, EXMC_NBL0

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
PE1	98	I/O	5VT	Default: PE1 Alternate: EXMC_NBL1
VSS_3	99	P	-	Default: VSS_3
VDD_3	100	P	-	Default: VDD_3

Notes:
1.Type: I= input, O = output, P = power.
2.I/O Level: 5VT = 5V tolerant.
3.Functions are available in GD32E103xx devices.

GD32E103Rx LQFP64 pin definitions

Table 2-4. GD32E103Rx LQFP64 pin definitions

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VBAT

Default: VBAT

PC13- TAMPER-

RTC

I/O

Default: PC13

Alternate: RTC_TAMPER

PC14-

OSC32IN

I/O

Default: PC14

Alternate:OSC32IN

PC15-

OSC32OUT

I/O

Default: PC15

Alternate:OSC32OUT

PD0-OSCIN

Default: OSCIN

Remap: PD0(3)

PD1-

OSCOUT

Default: OSCOUT

Remap: PD1(3)

NRST

I/O

Default: NRST

PC0

I/O

Default: PC0

Alternate: ADC01_IN10

PC1

I/O

Default: PC1

Alternate: ADC01_IN11

PC2

I/O

Default: PC2

Alternate: ADC01_IN12

PC3

I/O

Default: PC3

Alternate: ADC01_IN13

VSSA

Default: VSSA

VDDA

Default: VDDA

PA0-WKUP

I/O

Default: PA0

Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0_ETI, TIMER4_CH0, TIMER7_ETI

PA1

I/O

Default: PA1

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
				Alternate: USART1_RTS, ADC01_IN1, TIMER4_CH1,
				TIMER1_CH1
				Default: PA2
PA2	16	I/O	-	Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2,
				TIMER8_CH0, TIMER1_CH2, SPI0_IO2
				Default: PA3
PA3	17	I/O	-	Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3,
				TIMER1_CH3, TIMER8_CH1, SPI0_IO3
VSS_4	18	P	-	Default: VSS_4
VDD_4	19	P	-	Default: VDD_4
				Default: PA4
PA4	20	I/O	-	Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4
				Remap: SPI2_NSS, I2S2_WS
PA5	21	I/O	-	Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
				Default: PA6
PA6	22	I/O	-	Alternate: SPI0_MISO, TIMER7_BKIN, ADC01_IN6, TIMER2_CH0, TIMER12_CH0
				Remap: TIMER0_BKIN
				Default: PA7
PA7	23	I/O	-	Alternate: SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7, TIMER2_CH1, TIMER13_CH0
				Remap: TIMER0_CH0_ON
PC4	24	I/O	-	Default: PC4 Alternate: ADC01_IN14
PC5	25	I/O	-	Default: PC5 Alternate: ADC01_IN15
				Default: PB0
PB0	26	I/O	-	Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
				Remap: TIMER0_CH1_ON
				Default: PB1
PB1	27	I/O	-	Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
				Remap: TIMER0_CH2_ON
PB2	28	I/O	5VT	Default: PB2, BOOT1
				Default: PB10
PB10	29	I/O	5VT	Alternate: I2C1_SCL, USART2_TX
				Remap: TIMER1_CH2
				Default: PB11
PB11	30	I/O	5VT	Alternate: I2C1_SDA, USART2_RX
				Remap: TIMER1_CH3

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VSS_1

Default: VSS_1

VDD_1

Default: VDD_1

PB12

I/O

5VT

Default: PB12

Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, CAN1_RX

PB13

I/O

5VT

Default: PB13

Alternate: SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, CAN1_TX, I2C1_TXFRAME

PB14

I/O

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0

PB15

I/O

5VT

Default: PB15

Alternate: SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON, TIMER11_CH11

PC6

I/O

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

PC7

I/O

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

PC8

I/O

5VT

Default: PC8

Alternate: TIMER7_CH2 Remap: TIMER2_CH2

PC9

I/O

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

PA8

I/O

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC

PA9

I/O

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

PA10

I/O

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, V1REF

PA11

I/O

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

PA12

I/O

5VT

Default: PA12

Alternate: USART0_RTS, CAN0_TX, USBFS_DP, TIMER0_ETI

PA13

I/O

5VT

Default: JTMS, SWDIO

Remap: PA13

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

VSS_2

Default: VSS_2

VDD_2

Default: VDD_2

PA14

I/O

5VT

Default: JTCK, SWCLK

Remap:PA14

PA15

I/O

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0_ETI, TIMER1_ETI, PA15, SPI0_NSS

PC10

I/O

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

PC11

I/O

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

PC12

I/O

5VT

Default: PC12 Alternate: UART4_TX

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

PD2

I/O

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

PB3

I/O

5VT

Default: JTDO

Alternate: SPI2_SCK, I2S2_CK

Remap: TIMER1_CH1, PB3, TRACESWO, SPI0_SCK

PB4

I/O

5VT

Default: NJTRST

Alternate: SPI2_MISO, I2C0_TXFRAME Remap: TIMER2_CH0, PB4, SPI0_MISO

PB5

I/O

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

PB6

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX, SPI0_IO2

PB7

I/O

5VT

Default: PB7

Alternate: I2C0_SDA, TIMER3_CH1 Remap: USART0_RX, SPI0_IO3

BOOT0

Default: BOOT0

PB8

I/O

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0 Remap: I2C0_SCL, CAN0_RX

PB9

I/O

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0 Remap: I2C0_SDA, CAN0_TX

VSS_3

Default: VSS_3

Notes:
1.Type: I= input, O = output, P = power.
2.I/O Level: 5VT = 5V tolerant.
3.PD0/PD1 cannot be used for EXTI in this package.

ARM® Cortex™-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)

On-chip memory

Up to 128 Kbytes of Flash memory
Up to 32 KB of SRAM

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash at most, which includes code Flash that available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. An extra data Flash is also included for storing data mainly. Table 2-2. GD32E103xx memory map shows the memory of the GD32E103xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
1.71 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 120MHz. The maximum frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz. See Figure 2-6. GD32E103xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.66V/down to 1.62V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 1.71 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VDDA range: 1.71 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.71 to 3.6 V, power supply for RTC, external clock 32.768 KHz oscillator and backup registers (through power switch) when VDD is not present.

3.4.Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10).

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, IRC48M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, IRC48M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 3 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VREF- to VREF+
Temperature sensor

Up to two 12-bit 3 MSPS multi-channel ADCs are integrated in the device. It has a total of 18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT, VREFINT = 1.2V). The input voltage range is from VREF- to VREF+. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx, x=1, 2, 3) and the advanced timers (TIMER0 and TIMER7) with internal connection. The

temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

12-bit DAC with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC is used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.

DMA

7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 80 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 80 general purpose I/O pins (GPIO) in GD32E103xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)

The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge-aligned or center-aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 ~ TIMER4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~ TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 &TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32E103xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:

A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source

Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides several data transfer rates: up to 100 KHz of standard mode, up to 400 KHz of the fast mode and up to 1 MHz of the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)
SPI TI mode and NSS pulse mode supported

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 7.5MBits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication except UART4.

Inter-IC sound (I2S)

Two I2S bus interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32E103xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.

Universal serial bus full-speed interface (USBFS)

One full-speed USB Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator support crystal-less operation
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports

device modes. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal- less operation.

Controller area network (CAN)

Two CAN interface supports the CAN protocols version 2.0A, 2.0B, ISO11891-1:2015 and BOSCH CAN FD specification with communication frequency up to 1 Mbit/s of classic frames and 6 Mbit/s of FD frames
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash
Up to 16-bit data bus
?Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM®SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP100 (GD32E103Vx), LQFP64 (GD32E103Rx) and LQFP48 (GD32E103Cx) QFN36

(GD32E103Tx)
Operation temperature range: -40°C to +85°C (industrial level)

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飛睿無線定位測距uwb標(biāo)簽UWB芯片廠商UWB定位公司實現(xiàn)無縫定位的領(lǐng)跑者

在當(dāng)今數(shù)字化世界中，定位技術(shù)的重要性越來越被廣泛認(rèn)知和應(yīng)用。從室內(nèi)導(dǎo)航到物流跟蹤，無線測距UWB芯片的出現(xiàn)為各行各業(yè)帶來了新的可能性。而在這個充滿競爭的領(lǐng)域中，一家名為飛睿UWB定位公司的無線定位測距uwb標(biāo)簽UWB芯片廠商，憑借其先進(jìn)的技術(shù)和創(chuàng)新能力，成功成為實現(xiàn)無縫定位的先進(jìn)者。 UWB（Ultra-Wideband）是一種廣泛應(yīng)用于室內(nèi)定位和跟蹤的無線通信技術(shù)。相比傳統(tǒng)的定位技術(shù)，如GPS或Wi-Fi，UWB具有更高的精度和定位準(zhǔn)確性。這一技術(shù)利用短脈沖信號的傳播時間來計算物體與基站之間的距離，從而實現(xiàn)高精度的定位。飛睿UWB定位公司作為一家專注于UWB技術(shù)研發(fā)和應(yīng)用的企業(yè)，不僅在無線定位測距uwb標(biāo)簽UWB芯片領(lǐng)域擁有深厚的技術(shù)實力，而且在產(chǎn)品研發(fā)和市場推廣方面也積累了豐富的經(jīng)驗。該公司的核心業(yè)務(wù)包括UWB芯片的設(shè)計、制造、銷售和技術(shù)支持，并提供完整的解決方案來滿足不同行業(yè)的需求。一、UWB芯片的優(yōu)勢和應(yīng)用 UWB芯片作為實現(xiàn)準(zhǔn)確定位和跟蹤的關(guān)鍵技術(shù)，具有許多優(yōu)勢和廣泛應(yīng)用的潛力。首先，UWB芯片具有高精度的定位能力，可以達(dá)到亞厘米級的精度，尤其適用于對位置精度要求高的應(yīng)用場景。其次，UWB技術(shù)在室內(nèi)環(huán)境中的表現(xiàn)出色，能夠克服傳統(tǒng)技術(shù)在室內(nèi)多路徑干擾和信號衰減方面的限制。此外，UWB芯片還能夠?qū)崿F(xiàn)低功耗和高數(shù)據(jù)傳輸速率，適用于物流追蹤、室內(nèi)導(dǎo)航、智能家居等領(lǐng)域。二、飛睿UWB定位公司的研發(fā)實力和技術(shù)創(chuàng)新飛睿UWB定位公司以其突出的研發(fā)實力和技術(shù)創(chuàng)新能力在行業(yè)內(nèi)獨樹一幟。該公司擁有一支由工程師和科研人員組成的專業(yè)團(tuán)隊，致力于UWB芯片的研發(fā)和創(chuàng)新應(yīng)用。不僅在硬件設(shè)計方面有著豐富的經(jīng)驗，還在信號處理算法和定位算法等核心技術(shù)上有著深入研究。通過持續(xù)的技術(shù)創(chuàng)新和研發(fā)投入，UWB定位公司不斷地提升產(chǎn)品性能，滿足市場需求。三、UWB定位公司的產(chǎn)品與解決方案飛睿作為一家專業(yè)的無線定位測距uwb標(biāo)簽UWB芯片廠商，UWB定位公司提供了多款優(yōu)秀的產(chǎn)品與解決方案。首先，飛睿的UWB芯片具有高性能和可靠性，能夠滿足各行業(yè)對定位精度和穩(wěn)定性的要求。其次，UWB定位公司還提供完善的軟件開發(fā)工具和技術(shù)支持，幫助客戶快速集成和開發(fā)應(yīng)用。此外，UWB定位公司還定制化的解決方案，根據(jù)客戶的具體需求提供全面的技術(shù)支持和服務(wù)，確保系統(tǒng)的穩(wěn)定運行和良好的用戶體驗。四、UWB定位公司的應(yīng)用案例 UWB定位公司的產(chǎn)品和解決方案已經(jīng)成功應(yīng)用于多個行業(yè)，并取得了顯著的成果。以下是一些應(yīng)用案例的介紹： 1. 物流和倉儲管理：UWB定位技術(shù)可以實時追蹤貨物的位置和運動軌跡，提高物流效率和準(zhǔn)確性。通過在倉庫內(nèi)部安裝UWB基站，可以實現(xiàn)對貨物的高精度定位，減少貨物丟失和誤配的情況，提升倉儲管理的效率。 2. 室內(nèi)導(dǎo)航和定位服務(wù)：UWB芯片可以用于室內(nèi)導(dǎo)航和定位服務(wù)，幫助人們快速找到目的地并提供導(dǎo)航指引。在商場、機場、醫(yī)院等場所安裝UWB基站，可以提供準(zhǔn)確的導(dǎo)航服務(wù)，為用戶提供更好的體驗。 3. 車聯(lián)網(wǎng)和自動駕駛：UWB技術(shù)在車聯(lián)網(wǎng)和自動駕駛領(lǐng)域也有廣泛應(yīng)用。通過在車輛中安裝UWB傳感器和芯片，可以實現(xiàn)車輛之間的精準(zhǔn)通信和定位，提升駕駛安全性和車輛自主性。 4. 工業(yè)制造和機器人：在工業(yè)制造和機器人領(lǐng)域，UWB技術(shù)可以用于定位和跟蹤移動設(shè)備和機器人的位置，提高生產(chǎn)效率和自動化水平。通過與其他傳感器和系統(tǒng)的結(jié)合，可以實現(xiàn)更智能化的制造和操作。五、未來發(fā)展和挑戰(zhàn) 飛睿作為無線定位測距uwb標(biāo)簽UWB芯片廠商和定位技術(shù)提供商，UWB定位公司面臨著許多機遇和挑戰(zhàn)。隨著物聯(lián)網(wǎng)和人工智能的快速發(fā)展，對于精準(zhǔn)定位和跟蹤的需求將越來越大。UWB技術(shù)在室內(nèi)定位、智能交通、工業(yè)制造等領(lǐng)域有著廣闊的應(yīng)用前景。然而，市場競爭激烈，技術(shù)要求不斷提高，對于UWB定位公司來說，需要不斷加強技術(shù)研發(fā)和創(chuàng)新能力，提供更優(yōu)秀的產(chǎn)品和解決方案，贏得客戶的信任和市場份額。六、技術(shù)合作與生態(tài)建設(shè) 飛睿UWB定位公司在推動技術(shù)合作與生態(tài)建設(shè)方面也取得了顯著成績。他們積極與其他行業(yè)的廠商和合作伙伴進(jìn)行技術(shù)交流和合作，共同推動UWB技術(shù)的發(fā)展和應(yīng)用。通過與硬件設(shè)備生產(chǎn)商、軟件開發(fā)公司以及系統(tǒng)集成商等的合作，UWB定位公司不僅拓展了產(chǎn)品的應(yīng)用領(lǐng)域，還實現(xiàn)了技術(shù)的互補和資源的共享，加快了技術(shù)創(chuàng)新的速度和效果。七、用戶體驗與滿意度作為先進(jìn)的UWB芯片廠商和定位技術(shù)提供商，飛睿UWB定位公司一直將用戶體驗和滿意度放在優(yōu)先位置。他們注重產(chǎn)品的易用性和穩(wěn)定性，在產(chǎn)品設(shè)計和功能開發(fā)上持續(xù)優(yōu)化，以提供更好的用戶體驗。同時，UWB定位公司還建立了完善的售后服務(wù)體系，及時響應(yīng)客戶的需求和問題，并提供技術(shù)支持和解決方案，確保用戶能夠充分發(fā)揮UWB技術(shù)的價值和效果，獲得滿意的使用體驗。八、安全與隱私保護(hù) 在定位技術(shù)應(yīng)用的同時，飛睿UWB定位公司也重視用戶的安全和隱私保護(hù)。他們在產(chǎn)品設(shè)計和開發(fā)中注入了安全機制，采用加密和身份驗證等技術(shù)手段，確保用戶的數(shù)據(jù)和隱私得到有效保護(hù)。同時，UWB定位公司嚴(yán)格遵守相關(guān)法規(guī)和行業(yè)標(biāo)準(zhǔn)，保證數(shù)據(jù)的合法和合規(guī)使用，為用戶提供可信賴的定位解決方案。九、社會責(zé)任與可持續(xù)發(fā)展作為一家具有社會責(zé)任感的企業(yè)，飛睿uwb標(biāo)簽UWB定位公司積極關(guān)注可持續(xù)發(fā)展和環(huán)境保護(hù)。他們在生產(chǎn)過程中注重資源的合理利用和能源的節(jié)約，致力于減少對環(huán)境的影響。同時，UWB定位公司也積極參與社會公益活動，回饋社會，為推動可持續(xù)發(fā)展和社會進(jìn)步做出貢獻(xiàn)。總結(jié)：飛睿UWB定位公司作為一家先進(jìn)的無線定位測距uwb標(biāo)簽UWB芯片廠商和解決方案提供商，通過先進(jìn)的技術(shù)研發(fā)和創(chuàng)新能力，成功實現(xiàn)了無縫定位的先進(jìn)地位。他們的產(chǎn)品和解決方案在物流管理、室內(nèi)導(dǎo)航、車聯(lián)網(wǎng)、工業(yè)制造等領(lǐng)域展現(xiàn)出了巨大的應(yīng)用潛力和市場前景。同時，UWB定位公司注重用戶體驗和滿意度，積極推動技術(shù)合作與生態(tài)建設(shè)，關(guān)注安全與隱私保護(hù)，承擔(dān)社會責(zé)任，致力于可持續(xù)發(fā)展。相信在不久的將來，UWB定位公司將以其先進(jìn)的技術(shù)和卓越的服務(wù)，繼續(xù)引領(lǐng)無線測距UWB芯片領(lǐng)域的發(fā)展，為行業(yè)和用戶帶來更多的創(chuàng)新和價值。

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超寬帶 UWB Tag 開發(fā)兒童防丟器：守護(hù)孩子的安全天使

 發(fā)布時間： : 2024-09--27

在當(dāng)今社會，兒童的安全問題始終是家長們?yōu)殛P(guān)注的焦點之一。隨著科技的不斷進(jìn)步，各種創(chuàng)新的技術(shù)和產(chǎn)品應(yīng)運而生，旨在為孩子們提供更可靠的保護(hù)。其中，基于超寬帶 UWB Tag 技術(shù)開發(fā)的兒童防丟器無疑是一項具有突破性的創(chuàng)新成果。一、兒童走失問題的嚴(yán)峻性近年來，兒童走失的案例屢見不鮮，給無數(shù)家庭帶來了難以承受的痛苦和損失。據(jù)相關(guān)數(shù)據(jù)統(tǒng)計，我國每年走失的兒童數(shù)量高達(dá)數(shù)萬人，其中能夠成功找回的比例并不樂觀。這些走失的兒童可能遭遇拐賣、意外傷害甚至失去生命，每一個案例都讓人痛心疾首。造成兒童走失的原因多種多樣，有的是因為家長的疏忽大意，有的是因為孩子在陌生環(huán)境中迷失方向，還有的是遭遇了不法分子的拐騙。無論是哪種情況，都凸顯了加強兒童安全保護(hù)的緊迫性和重要性。二、超寬帶 UWB Tag 技術(shù)簡介超寬帶 UWB（Ultra-WideBand）技術(shù)是一種新型的無線通信技術(shù)，具有高精度定位、低功耗、強抗干擾等諸多優(yōu)點。UWB Tag 則是基于 UWB 技術(shù)的一種小型設(shè)備，可以實現(xiàn)對物體或人員的精準(zhǔn)定位和跟蹤。與傳統(tǒng)的定位技術(shù)如 GPS 相比，UWB 技術(shù)在室內(nèi)環(huán)境中的定位精度可以達(dá)到厘米級別，能夠準(zhǔn)確地確定兒童的位置。而且，UWB 信號具有很強的穿透能力，可以穿過墻壁、障礙物等，不受環(huán)境因素的影響。此外，UWB 技術(shù)的功耗非常低，UWB Tag 可以長時間工作，無需頻繁充電或更換電池。三、基于超寬帶 UWB Tag 開發(fā)的兒童防丟器的工作原理基于超寬帶 UWB Tag 開發(fā)的兒童防丟器通常由兩部分組成：一個佩戴在兒童身上的 UWB Tag 標(biāo)簽，以及家長手中的接收終端（如手機 APP 或?qū)Ｓ迷O(shè)備）。當(dāng)兒童佩戴的 UWB Tag 標(biāo)簽與家長手中的接收終端處于有效范圍內(nèi)時，接收終端可以實時獲取 UWB Tag 標(biāo)簽的位置信息，并通過地圖、語音提示等方式向家長展示孩子的位置。一旦兒童超出了預(yù)設(shè)的安全范圍，接收終端會立即發(fā)出警報，提醒家長注意。在實際工作中，UWB Tag 標(biāo)簽會不斷向周圍發(fā)送超寬帶脈沖信號，這些信號被附近的基站或接收設(shè)備接收后，通過復(fù)雜的算法計算出標(biāo)簽的位置坐標(biāo)。由于 UWB 信號的傳播速度快，且具有納秒級的時間分辨率，因此可以實現(xiàn)高精度的定位。四、兒童防丟器的功能特點 1. 實時定位與追蹤 ? ? - 家長可以通過手機 APP 或?qū)Ｓ迷O(shè)備隨時隨地查看孩子的實時位置，了解孩子的行蹤。 ? ? - 定位精度高達(dá)厘米級別，能夠準(zhǔn)確地確定孩子在室內(nèi)、室外的具體位置。 2. 安全區(qū)域設(shè)定 ? ? - 家長可以根據(jù)實際情況，在地圖上劃定安全區(qū)域，如學(xué)校、小區(qū)、公園等。 ? ? - 當(dāng)孩子離開安全區(qū)域時，防丟器會自動發(fā)出警報，提醒家長。 3. 雙向通話與語音提醒 ? ? - 兒童防丟器通常配備雙向通話功能，家長可以與孩子進(jìn)行通話，了解孩子的情況。 ? ? - 同時，家長也可以通過手機 APP 向孩子發(fā)送語音提醒，如“不要亂跑”、“注意安全”等。 4. 歷史軌跡查詢 ? ? - 系統(tǒng)會自動記錄孩子的活動軌跡，家長可以查詢歷史軌跡，了解孩子的日常活動范圍和習(xí)慣。 5. 低功耗與長續(xù)航 ? ? - 采用先進(jìn)的低功耗技術(shù)，UWB Tag 標(biāo)簽可以持續(xù)工作數(shù)天甚至數(shù)周，無需頻繁充電。 6. 小巧輕便與佩戴舒適 ? ? - 兒童防丟器的設(shè)計通?？紤]到孩子的佩戴感受，小巧輕便，不會給孩子帶來負(fù)擔(dān)。 ? ? - 可以選擇佩戴在手腕、書包、衣服等部位，方便且不易丟失。五、兒童防丟器的應(yīng)用場景 1. 學(xué)校與幼兒園 ? ? - 在學(xué)校和幼兒園中，孩子們的活動范圍較大，容易出現(xiàn)走失的情況。佩戴兒童防丟器可以讓老師和家長隨時了解孩子的位置，保障孩子的安全。 2. 商場與超市 ? ? - 商場和超市是人流量較大的場所，孩子容易被各種商品吸引而離開家長的視線。佩戴兒童防丟器可以讓家長在第一時間發(fā)現(xiàn)孩子的走失情況，并迅速找到孩子。 3. 公園與游樂場 ? ? - 公園和游樂場是孩子們玩耍的好去處，但也是容易發(fā)生意外的地方。佩戴兒童防丟器可以讓家長放心讓孩子玩耍，同時能夠及時應(yīng)對突發(fā)情況。 4. 旅游與出行 ? ? - 在外出旅游或乘坐公共交通工具時，孩子可能會因為好奇而離開家長身邊。佩戴兒童防丟器可以讓家長在陌生的環(huán)境中更好地照顧孩子，確保孩子的安全。六、選擇兒童防丟器時需要考慮的因素 1. 定位精度 ? ? - 定位精度是衡量兒童防丟器性能的重要指標(biāo)，越高的定位精度意味著能夠更準(zhǔn)確地找到孩子的位置。 2. 續(xù)航能力 ? ? - 續(xù)航能力直接影響兒童防丟器的使用體驗，如果需要頻繁充電或更換電池，會給家長帶來不便。 3. 佩戴舒適度 ? ? - 孩子需要長時間佩戴防丟器，因此佩戴舒適度至關(guān)重要。選擇材質(zhì)柔軟、重量輕、設(shè)計合理的產(chǎn)品，可以減少孩子的抵觸情緒。 4. 功能多樣性 ? ? - 除了基本的定位功能外，雙向通話、語音提醒、安全區(qū)域設(shè)定等功能可以為家長提供更多的便利和保障。 5. 品牌信譽與售后服務(wù) ? ? - 選擇品牌和有良好售后服務(wù)的產(chǎn)品，可以保證產(chǎn)品的質(zhì)量和使用過程中的問題能夠得到及時解決。七、兒童防丟器的發(fā)展趨勢隨著技術(shù)的不斷進(jìn)步和市場需求的增加，兒童防丟器未來將呈現(xiàn)出以下發(fā)展趨勢： 1. 智能化 ? ? - 結(jié)合人工智能技術(shù)，兒童防丟器將能夠更加智能地分析孩子的行為模式和潛在風(fēng)險，提前發(fā)出預(yù)警。 2. 多模融合 ? ? - 將 UWB 技術(shù)與其他定位技術(shù)（如 GPS、北斗等）融合，實現(xiàn)更廣泛、更精準(zhǔn)的定位。 3. 與物聯(lián)網(wǎng)的結(jié)合 ? ? - 與智能家居、智能穿戴設(shè)備等物聯(lián)網(wǎng)設(shè)備互聯(lián)互通，形成更加完善的安全防護(hù)體系。 4. 個性化定制 ? ? - 根據(jù)不同家庭和孩子的需求，提供個性化的功能和服務(wù)，滿足多樣化的市場需求。八、總結(jié) 兒童是家庭的希望，是社會的未來。保障兒童的安全是我們每個人的責(zé)任。基于超寬帶 UWB Tag 技術(shù)開發(fā)的兒童防丟器為家長們提供了一種全新的、高效的兒童安全保護(hù)手段。在選擇兒童防丟器時，家長們應(yīng)該綜合考慮定位精度、續(xù)航能力、佩戴舒適度、功能多樣性等因素，選擇適合自己孩子的產(chǎn)品。相信隨著技術(shù)的不斷發(fā)展和創(chuàng)新，兒童防丟器將越來越完善，為孩子們的安全保駕護(hù)航。讓我們共同努力，為孩子們創(chuàng)造一個安全、快樂的成長環(huán)境，讓每一個孩子都能在陽光下健康成長！

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