兆易創(chuàng)新GD32F103RCT6-GD32 ARM Cortex-M3 Microcontroller
兆易創(chuàng)新GD32F103RCT6-GD32 ARM Cortex-M3 Microcontroller
GigaDevice Semiconductor Inc.
GD32F103xx
ARM® Cortex™-M3 32-bit MCU
Datasheet
General description
The GD32F103xx device is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F103xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general 16-bit timers, two basic timers plus two PWM advanced timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, an USBD, a CAN and a SDIO.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F103xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, video intercom, PC peripherals and so on.
Device information
Table 2-1. GD32F103xx devices features and peripheral list
|
Part Number |
GD32F103xx |
||||||||||||||
|
|
T4 |
T6 |
T8 |
TB |
C4 |
C6 |
C8 |
CB |
R4 |
R6 |
R8 |
RB |
V8 |
VB |
|
|
Flash (KB) |
16 |
32 |
64 |
128 |
16 |
32 |
64 |
128 |
16 |
32 |
64 |
128 |
64 |
128 |
|
|
SRAM (KB) |
6 |
10 |
20 |
20 |
6 |
10 |
20 |
20 |
6 |
10 |
20 |
20 |
20 |
20 |
|
|
Timers |
General timer(16- bit) |
2 (1-2) |
2 (1-2) |
3 (1-3) |
3 (1-3) |
2 (1-2) |
2 (1-2) |
3 (1-3) |
3 (1-3) |
2 (1-2) |
2 (1-2) |
3 (1-3) |
3 (1-3) |
3 (1-3) |
3 (1-3) |
|
|
Advanced timer(16- bit) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
|
|
SysTick |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
Watchdog |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
RTC |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
Connectivity |
USART |
2 (0-1) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
3 (0-2) |
3 (0-2) |
2 (0-1) |
2 (0-1) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
|
|
I2C |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
2 (0-1) |
2 (0-1) |
1 (0) |
1 (0) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
|
|
SPI |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
2 (0-1) |
2 (0-1) |
1 (0) |
1 (0) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
2 (0-1) |
|
|
CAN |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
USBD |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
GPIO |
26 |
26 |
26 |
26 |
37 |
37 |
37 |
37 |
51 |
51 |
51 |
51 |
80 |
80 |
|
|
EXMC |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
|
|
EXTI |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
|
|
ADC |
Units |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
Channels |
10 |
10 |
10 |
10 |
10 |
10 |
10 |
10 |
16 |
16 |
16 |
16 |
16 |
16 |
|
Package |
QFN36 |
LQFP48 |
LQFP64 |
LQFP100 |
|||||||||||
|
|
GD32F103xx |
||||||||||||||
|
|
RC |
RD |
RE |
RF |
RG |
RI |
RK |
VC |
VD |
VE |
VF |
VG |
VI |
VK |
|
|
Flash (KB) |
256 |
384 |
512 |
768 |
1024 |
2048 |
3072 |
256 |
384 |
512 |
768 |
1024 |
2048 |
3072 |
|
|
SRAM (KB) |
48 |
64 |
64 |
96 |
96 |
96 |
96 |
48 |
64 |
64 |
96 |
96 |
96 |
96 |
|
|
Timers |
General timer(16- bit) |
4 (1-4) |
4 (1-4) |
4 (1-4) |
10 (1-4,8-13) |
10 (1-4,8-13) |
10 (1-4,8-13) |
10 (1-4,8-13) |
4 (1-4) |
4 (1-4) |
4 (1-4) |
10 (1-4,8-13) |
10 (1-4,8-13) |
10 (1-4,8-13) |
10 (1-4,8-13) |
|
|
Advanced timer(16- bit) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
|
|
SysTick |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
Basic timer(16- bit) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
|
|
Watchdog |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
RTC |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
Connectivity |
USART |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
|
|
UART |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
I2C |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
SPI |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
|
|
CAN |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
USBD |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
I2S |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
|
|
SDIO |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
GPIO |
51 |
51 |
51 |
51 |
51 |
51 |
51 |
80 |
80 |
80 |
80 |
80 |
80 |
80 |
|
|
EXMC |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
EXTI |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
|
|
ADC |
Units |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
|
|
Channels |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
|
DAC |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
Package |
LQFP64 |
LQFP100 |
|||||||||||||
|
Part Number |
GD32F103xx |
||||||||
|
|
ZC |
ZD |
ZE |
ZF |
ZG |
ZI |
ZK |
||
|
Flash (KB) |
256 |
384 |
512 |
768 |
1024 |
2048 |
3072 |
||
|
SRAM (KB) |
48 |
64 |
64 |
96 |
96 |
96 |
96 |
||
|
Timers |
General timer(16-bit) |
4 (1-4) |
4 (1-4) |
4 (1-4) |
10 (1-4,8-13) |
10 (1-4,8-13) |
10 (1-4,8-13) |
10 (1-4,8-13) |
|
|
|
Advanced timer(16-bit) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
2 (0,7) |
|
|
|
SysTick |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
|
Basic timer(16- bit) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
2 (5-6) |
|
|
|
Watchdog |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
|
RTC |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
Connectivity |
USART |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
|
|
|
UART |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
|
I2C |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
|
|
SPI |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
3 (0-2) |
|
|
|
CAN |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
|
USBD |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
|
I2S |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
2 (1-2) |
|
|
|
SDIO |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
|
GPIO |
112 |
112 |
112 |
112 |
112 |
112 |
112 |
||
|
EXMC |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
||
|
EXTI |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
||
|
ADC |
Units |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
|
|
|
Channels |
21 |
21 |
21 |
21 |
21 |
21 |
21 |
|
|
DAC |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
||
|
Package |
LQFP144 |
||||||||
Memory map
Table 2-4. GD32F103xx memory map
|
Pre-defined Regions |
Bus |
Address |
Peripherals |
|
External device |
AHB |
0xA000 0000 - 0xA000 0FFF |
EXMC - SWREG |
|
External RAM |
|
0x9000 0000 - 0x9FFF FFFF |
EXMC - PC CARD |
|
|
|
0x7000 0000 - 0x8FFF FFFF |
EXMC - NAND |
|
|
|
0x6000 0000 - 0x6FFF FFFF |
EXMC - NOR/PSRAM/SRA M |
|
Peripheral |
AHB |
0x5000 0000 - 0x5003 FFFF |
Reserved |
|
|
|
0x4008 0000 - 0x4FFF FFFF |
Reserved |
|
|
|
0x4004 0000 - 0x4007 FFFF |
Reserved |
|
|
|
0x4002 BC00 - 0x4003 FFFF |
Reserved |
|
|
|
0x4002 B000 - 0x4002 BBFF |
Reserved |
|
|
|
0x4002 A000 - 0x4002 AFFF |
Reserved |
|
|
|
0x4002 8000 - 0x4002 9FFF |
Reserved |
|
|
|
0x4002 6800 - 0x4002 7FFF |
Reserved |
|
|
|
0x4002 6400 - 0x4002 67FF |
Reserved |
|
|
|
0x4002 6000 - 0x4002 63FF |
Reserved |
|
|
|
0x4002 5000 - 0x4002 5FFF |
Reserved |
|
|
|
0x4002 4000 - 0x4002 4FFF |
Reserved |
|
|
|
0x4002 3C00 - 0x4002 3FFF |
Reserved |
|
|
|
0x4002 3800 - 0x4002 3BFF |
Reserved |
|
|
|
0x4002 3400 - 0x4002 37FF |
Reserved |
|
|
|
0x4002 3000 - 0x4002 33FF |
CRC |
|
|
|
0x4002 2C00 - 0x4002 2FFF |
Reserved |
|
|
|
0x4002 2800 - 0x4002 2BFF |
Reserved |
|
|
|
0x4002 2400 - 0x4002 27FF |
Reserved |
|
|
|
0x4002 2000 - 0x4002 23FF |
FMC |
|
|
|
0x4002 1C00 - 0x4002 1FFF |
Reserved |
|
|
|
0x4002 1800 - 0x4002 1BFF |
Reserved |
|
|
|
0x4002 1400 - 0x4002 17FF |
Reserved |
|
|
|
0x4002 1000 - 0x4002 13FF |
RCU |
|
|
|
0x4002 0C00 - 0x4002 0FFF |
Reserved |
|
|
|
0x4002 0800 - 0x4002 0BFF |
Reserved |
|
|
|
0x4002 0400 - 0x4002 07FF |
DMA1 |
|
|
|
0x4002 0000 - 0x4002 03FF |
DMA0 |
|
|
|
0x4001 8400 - 0x4001 FFFF |
Reserved |
|
Pre-defined Regions |
Bus |
Address |
Peripherals |
|
|
|
0x4001 8000 - 0x4001 83FF |
SDIO |
|
|
APB2 |
0x4001 7C00 - 0x4001 7FFF |
Reserved |
|
|
|
0x4001 7800 - 0x4001 7BFF |
Reserved |
|
|
|
0x4001 7400 - 0x4001 77FF |
Reserved |
|
|
|
0x4001 7000 - 0x4001 73FF |
Reserved |
|
|
|
0x4001 6C00 - 0x4001 6FFF |
Reserved |
|
|
|
0x4001 6800 - 0x4001 6BFF |
Reserved |
|
|
|
0x4001 5C00 - 0x4001 67FF |
Reserved |
|
|
|
0x4001 5800 - 0x4001 5BFF |
Reserved |
|
|
|
0x4001 5400 - 0x4001 57FF |
TIMER10 |
|
|
|
0x4001 5000 - 0x4001 53FF |
TIMER9 |
|
|
|
0x4001 4C00 - 0x4001 4FFF |
TIMER8 |
|
|
|
0x4001 4800 - 0x4001 4BFF |
Reserved |
|
|
|
0x4001 4400 - 0x4001 47FF |
Reserved |
|
|
|
0x4001 4000 - 0x4001 43FF |
Reserved |
|
|
|
0x4001 3C00 - 0x4001 3FFF |
ADC2 |
|
|
|
0x4001 3800 - 0x4001 3BFF |
USART0 |
|
|
|
0x4001 3400 - 0x4001 37FF |
TIMER7 |
|
|
|
0x4001 3000 - 0x4001 33FF |
SPI0 |
|
|
|
0x4001 2C00 - 0x4001 2FFF |
TIMER0 |
|
|
|
0x4001 2800 - 0x4001 2BFF |
ADC1 |
|
|
|
0x4001 2400 - 0x4001 27FF |
ADC0 |
|
|
|
0x4001 2000 - 0x4001 23FF |
GPIOG |
|
|
|
0x4001 1C00 - 0x4001 1FFF |
GPIOF |
|
|
|
0x4001 1800 - 0x4001 1BFF |
GPIOE |
|
|
|
0x4001 1400 - 0x4001 17FF |
GPIOD |
|
|
|
0x4001 1000 - 0x4001 13FF |
GPIOC |
|
|
|
0x4001 0C00 - 0x4001 0FFF |
GPIOB |
|
|
|
0x4001 0800 - 0x4001 0BFF |
GPIOA |
|
|
|
0x4001 0400 - 0x4001 07FF |
EXTI |
|
|
|
0x4001 0000 - 0x4001 03FF |
AFIO |
|
|
APB1 |
0x4000 CC00 - 0x4000 FFFF |
Reserved |
|
|
|
0x4000 C800 - 0x4000 CBFF |
Reserved |
|
|
|
0x4000 C400 - 0x4000 C7FF |
Reserved |
|
|
|
0x4000 C000 - 0x4000 C3FF |
Reserved |
|
|
|
0x4000 8000 - 0x4000 BFFF |
Reserved |
|
|
|
0x4000 7C00 - 0x4000 7FFF |
Reserved |
|
|
|
0x4000 7800 - 0x4000 7BFF |
Reserved |
|
|
|
0x4000 7400 - 0x4000 77FF |
DAC |
|
|
|
0x4000 7000 - 0x4000 73FF |
PMU |
|
Pre-defined Regions |
Bus |
Address |
Peripherals |
|
|
|
0x4000 6C00 - 0x4000 6FFF |
BKP |
|
|
|
0x4000 6800 - 0x4000 6BFF |
Reserved |
|
|
|
0x4000 6400 - 0x4000 67FF |
CAN0 |
|
|
|
0x4000 6000 - 0x4000 63FF |
Shared USBD/CAN SRAM 512 bytes |
|
|
|
0x4000 5C00 - 0x4000 5FFF |
USBD |
|
|
|
0x4000 5800 - 0x4000 5BFF |
I2C1 |
|
|
|
0x4000 5400 - 0x4000 57FF |
I2C0 |
|
|
|
0x4000 5000 - 0x4000 53FF |
UART4 |
|
|
|
0x4000 4C00 - 0x4000 4FFF |
UART3 |
|
|
|
0x4000 4800 - 0x4000 4BFF |
USART2 |
|
|
|
0x4000 4400 - 0x4000 47FF |
USART1 |
|
|
|
0x4000 4000 - 0x4000 43FF |
Reserved |
|
|
|
0x4000 3C00 - 0x4000 3FFF |
SPI2/I2S2 |
|
|
|
0x4000 3800 - 0x4000 3BFF |
SPI1/I2S1 |
|
|
|
0x4000 3400 - 0x4000 37FF |
Reserved |
|
|
|
0x4000 3000 - 0x4000 33FF |
FWDGT |
|
|
|
0x4000 2C00 - 0x4000 2FFF |
WWDGT |
|
|
|
0x4000 2800 - 0x4000 2BFF |
RTC |
|
|
|
0x4000 2400 - 0x4000 27FF |
Reserved |
|
|
|
0x4000 2000 - 0x4000 23FF |
TIMER13 |
|
|
|
0x4000 1C00 - 0x4000 1FFF |
TIMER12 |
|
|
|
0x4000 1800 - 0x4000 1BFF |
TIMER11 |
|
|
|
0x4000 1400 - 0x4000 17FF |
TIMER6 |
|
|
|
0x4000 1000 - 0x4000 13FF |
TIMER5 |
|
|
|
0x4000 0C00 - 0x4000 0FFF |
TIMER4 |
|
|
|
0x4000 0800 - 0x4000 0BFF |
TIMER3 |
|
|
|
0x4000 0400 - 0x4000 07FF |
TIMER2 |
|
|
|
0x4000 0000 - 0x4000 03FF |
TIMER1 |
|
SRAM |
AHB |
0x2007 0000 - 0x3FFF FFFF |
Reserved |
|
|
|
0x2006 0000 - 0x2006 FFFF |
Reserved |
|
|
|
0x2003 0000 - 0x2005 FFFF |
Reserved |
|
|
|
0x2002 0000 - 0x2002 FFFF |
Reserved |
|
|
|
0x2001 C000 - 0x2001 FFFF |
Reserved |
|
|
|
0x2001 8000 - 0x2001 BFFF |
Reserved |
|
|
|
0x2000 0000 - 0x2001 7FFF |
SRAM |
|
Code |
AHB |
0x1FFF F810 - 0x1FFF FFFF |
Reserved |
|
|
|
0x1FFF F800 - 0x1FFF F80F |
Option Bytes |
|
|
|
0x1FFF B000 - 0x1FFF F7FF |
Boot loader |
|
|
|
0x1FFF 7A10 - 0x1FFF AFFF |
Reserved |
|
Pre-defined Regions |
Bus |
Address |
Peripherals |
|
|
|
0x1FFF 7800 - 0x1FFF 7A0F |
Reserved |
|
|
|
0x1FFF 0000 - 0x1FFF 77FF |
Reserved |
|
|
|
0x1FFE C010 - 0x1FFE FFFF |
Reserved |
|
|
|
0x1FFE C000 - 0x1FFE C00F |
Reserved |
|
|
|
0x1001 0000 - 0x1FFE BFFF |
Reserved |
|
|
|
0x1000 0000 - 0x1000 FFFF |
Reserved |
|
|
|
0x083C 0000 - 0x0FFF FFFF |
Reserved |
|
|
|
0x0830 0000 - 0x083B FFFF |
Reserved |
|
|
|
0x0800 0000 - 0x082F FFFF |
Main Flash |
|
|
|
0x0030 0000 - 0x07FF FFFF |
Reserved |
|
|
|
0x0000 0000 - 0x002F FFFF |
Aliased to Main Flash or Boot loader |
GD32F103Zx LQFP144 pin definitions
Table 2-5. GD32F103Zx LQFP144 pin definitions
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
PE2 |
1 |
I/O |
5VT |
Default: PE2 Alternate: TRACECK, EXMC_A23 |
|
PE3 |
2 |
I/O |
5VT |
Default: PE3 Alternate: TRACED0, EXMC_A19 |
|
PE4 |
3 |
I/O |
5VT |
Default: PE4 Alternate:TRACED1, EXMC_A20 |
|
PE5 |
4 |
I/O |
5VT |
Default: PE5 Alternate:TRACED2, EXMC_A21 Remap: TIMER8_CH0(3) |
|
PE6 |
5 |
I/O |
5VT |
Default: PE6 Alternate:TRACED3, EXMC_A22 Remap: TIMER8_CH1(3) |
|
VBAT |
6 |
P |
|
Default: VBAT |
|
PC13- TAMPER- RTC |
7 |
I/O |
|
Default: PC13 Alternate: TAMPER-RTC |
|
PC14- OSC32IN |
8 |
I/O |
|
Default: PC14 Alternate: OSC32IN |
|
PC15- OSC32OUT |
9 |
I/O |
|
Default: PC15 Alternate: OSC32OUT |
|
PF0 |
10 |
I/O |
5VT |
Default: PF0 Alternate: EXMC_A0 |
|
PF1 |
11 |
I/O |
5VT |
Default: PF1 Alternate: EXMC_A1 |
|
PF2 |
12 |
I/O |
5VT |
Default: PF2 Alternate: EXMC_A2 |
|
PF3 |
13 |
I/O |
5VT |
Default: PF3 Alternate: EXMC_A3 |
|
PF4 |
14 |
I/O |
5VT |
Default: PF4 Alternate: EXMC_A4 |
|
PF5 |
15 |
I/O |
5VT |
Default: PF5 Alternate: EXMC_A5 |
|
VSS_5 |
16 |
P |
|
Default: VSS_5 |
|
VDD_5 |
17 |
P |
|
Default: VDD_5 |
|
PF6 |
18 |
I/O |
|
Default: PF6 |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
|
Alternate: ADC2_IN4, EXMC_NIORD Remap: TIMER9_CH0(3) |
|
PF7 |
19 |
I/O |
|
Default: PF7 Alternate: ADC2_IN5, EXMC_NREG Remap: TIMER10_CH0(3) |
|
PF8 |
20 |
I/O |
|
Default: PF8 Alternate: ADC2_IN6, EXMC_NIOWR Remap: TIMER12_CH0(3) |
|
PF9 |
21 |
I/O |
|
Default: PF9 Alternate: ADC2_IN7, EXMC_CD Remap: TIMER13_CH0(3) |
|
PF10 |
22 |
I/O |
|
Default: PF10 Alternate: ADC2_IN8, EXMC_INTR |
|
OSCIN |
23 |
I |
|
Default: OSCIN Remap: PD0 |
|
OSCOUT |
24 |
O |
|
Default: OSCOUT Remap: PD1 |
|
NRST |
25 |
I/O |
|
Default: NRST |
|
PC0 |
26 |
I/O |
|
Default: PC0 Alternate: ADC012_IN10 |
|
PC1 |
27 |
I/O |
|
Default: PC1 Alternate: ADC012_IN11 |
|
PC2 |
28 |
I/O |
|
Default: PC2 Alternate: ADC012_IN12 |
|
PC3 |
29 |
I/O |
|
Default: PC3 Alternate: ADC012_IN13 |
|
VSSA |
30 |
P |
|
Default: VSSA |
|
VREF- |
31 |
P |
|
Default: VREF- |
|
VREF+ |
32 |
P |
|
Default: VREF+ |
|
VDDA |
33 |
P |
|
Default: VDDA |
|
PA0-WKUP |
34 |
I/O |
|
Default: PA0 Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI |
|
PA1 |
35 |
I/O |
|
Default: PA1 Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1 |
|
PA2 |
36 |
I/O |
|
Default: PA2 Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0(3) |
|
PA3 |
37 |
I/O |
|
Default: PA3 Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1(3) |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
VSS_4 |
38 |
P |
|
Default: VSS_4 |
|
VDD_4 |
39 |
P |
|
Default: VDD_4 |
|
PA4 |
40 |
I/O |
|
Default: PA4 Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0 Remap:SPI2_NSS, I2S2_WS |
|
PA5 |
41 |
I/O |
|
Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 |
|
PA6 |
42 |
I/O |
|
Default: PA6 Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN, TIMER12_CH0(3) Remap: TIMER0_BRKIN |
|
PA7 |
43 |
I/O |
|
Default: PA7 Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON, TIMER13_CH0(3) Remap: TIMER0_CH0_ON |
|
PC4 |
44 |
I/O |
|
Default: PC4 Alternate: ADC01_IN14 |
|
PC5 |
45 |
I/O |
|
Default: PC5 Alternate: ADC01_IN15 |
|
PB0 |
46 |
I/O |
|
Default: PB0 Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON Remap: TIMER0_CH1_ON |
|
PB1 |
47 |
I/O |
|
Default: PB1 Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON Remap: TIMER0_CH2_ON |
|
PB2 |
48 |
I/O |
5VT |
Default: PB2, BOOT1 |
|
PF11 |
49 |
I/O |
5VT |
Default: PF11 Alternate: EXMC_NIOS16 |
|
PF12 |
50 |
I/O |
5VT |
Default: PF12 Alternate: EXMC_A6 |
|
VSS_6 |
51 |
P |
|
Default: VSS_6 |
|
VDD_6 |
52 |
P |
|
Default: VDD_6 |
|
PF13 |
53 |
I/O |
5VT |
Default: PF13 Alternate: EXMC_A7 |
|
PF14 |
54 |
I/O |
5VT |
Default: PF14 Alternate: EXMC_A8 |
|
PF15 |
55 |
I/O |
5VT |
Default: PF15 Alternate: EXMC_A9 |
|
PG0 |
56 |
I/O |
5VT |
Default: PG0 Alternate: EXMC_A10 |
|
PG1 |
57 |
I/O |
5VT |
Default: PG1 |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
|
Alternate: EXMC_A11 |
|
PE7 |
58 |
I/O |
5VT |
Default: PE7 Alternate: EXMC_D4 Remap: TIMER0_ETI |
|
PE8 |
59 |
I/O |
5VT |
Default: PE8 Alternate: EXMC_D5 Remap: TIMER0_CH0_ON |
|
PE9 |
60 |
I/O |
5VT |
Default: PE9 Alternate: EXMC_D6 Remap: TIMER0_CH0 |
|
VSS_7 |
61 |
P |
|
Default: VSS_7 |
|
VDD_7 |
62 |
P |
|
Default: VDD_7 |
|
PE10 |
63 |
I/O |
5VT |
Default: PE10 Alternate: EXMC_D7 Remap: TIMER0_CH1_ON |
|
PE11 |
64 |
I/O |
5VT |
Default: PE11 Alternate: EXMC_D8 Remap: TIMER0_CH1 |
|
PE12 |
65 |
I/O |
5VT |
Default: PE12 Alternate: EXMC_D9 Remap: TIMER0_CH2_ON |
|
PE13 |
66 |
I/O |
5VT |
Default: PE13 Alternate: EXMC_D10 Remap: TIMER0_CH2 |
|
PE14 |
67 |
I/O |
5VT |
Default: PE14 Alternate: EXMC_D11 Remap: TIMER0_CH3 |
|
PE15 |
68 |
I/O |
5VT |
Default: PE15 Alternate: EXMC_D12 Remap: TIMER0_BRKIN |
|
PB10 |
69 |
I/O |
5VT |
Default: PB10 Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 |
|
PB11 |
70 |
I/O |
5VT |
Default: PB11 Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 |
|
VSS_1 |
71 |
P |
|
Default: VSS_1 |
|
VDD_1 |
72 |
P |
|
Default: VDD_1 |
|
PB12 |
73 |
I/O |
5VT |
Default: PB12 Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS |
|
PB13 |
74 |
I/O |
5VT |
Default: PB13 |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
|
Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK |
|
PB14 |
75 |
I/O |
5VT |
Default: PB14 Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0(3) |
|
PB15 |
76 |
I/O |
5VT |
Default: PB15 Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1(3) |
|
PD8 |
77 |
I/O |
5VT |
Default: PD8 Alternate: EXMC_D13 Remap: USART2_TX |
|
PD9 |
78 |
I/O |
5VT |
Default: PD9 Alternate: EXMC_D14 Remap: USART2_RX |
|
PD10 |
79 |
I/O |
5VT |
Default: PD10 Alternate: EXMC_D15 Remap: USART2_CK |
|
PD11 |
80 |
I/O |
5VT |
Default: PD11 Alternate: EXMC_A16 Remap: USART2_CTS |
|
PD12 |
81 |
I/O |
5VT |
Default: PD12 Alternate: EXMC_A17 Remap: TIMER3_CH0, USART2_RTS |
|
PD13 |
82 |
I/O |
5VT |
Default: PD13 Alternate: EXMC_A18 Remap: TIMER3_CH1 |
|
VSS_8 |
83 |
P |
|
Default: VSS_8 |
|
VDD_8 |
84 |
P |
|
Default: VDD_8 |
|
PD14 |
85 |
I/O |
5VT |
Default: PD14 Alternate: EXMC_D0 Remap: TIMER3_CH2 |
|
PD15 |
86 |
I/O |
5VT |
Default: PD15 Alternate: EXMC_D1 Remap: TIMER3_CH3 |
|
PG2 |
87 |
I/O |
5VT |
Default: PG2 Alternate: EXMC_A12 |
|
PG3 |
88 |
I/O |
5VT |
Default: PG3 Alternate: EXMC_A13 |
|
PG4 |
89 |
I/O |
5VT |
Default: PG4 Alternate: EXMC_A14 |
|
PG5 |
90 |
I/O |
5VT |
Default: PG5 Alternate: EXMC_A15 |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
PG6 |
91 |
I/O |
5VT |
Default: PG6 Alternate: EXMC_INT1 |
|
PG7 |
92 |
I/O |
5VT |
Default: PG7 Alternate: EXMC_INT2 |
|
PG8 |
93 |
I/O |
5VT |
Default: PG8 |
|
VSS_9 |
94 |
P |
|
Default: VSS_9 |
|
VDD_9 |
95 |
P |
|
Default: VDD_9 |
|
PC6 |
96 |
I/O |
5VT |
Default: PC6 Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6 Remap: TIMER2_CH0 |
|
PC7 |
97 |
I/O |
5VT |
Default: PC7 Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7 Remap: TIMER2_CH1 |
|
PC8 |
98 |
I/O |
5VT |
Default: PC8 Alternate: TIMER7_CH2, SDIO_D0 Remap: TIMER2_CH2 |
|
PC9 |
99 |
I/O |
5VT |
Default: PC9 Alternate: TIMER7_CH3, SDIO_D1 Remap: TIMER2_CH3 |
|
PA8 |
100 |
I/O |
5VT |
Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0 |
|
PA9 |
101 |
I/O |
5VT |
Default: PA9 Alternate: USART0_TX, TIMER0_CH1 |
|
PA10 |
102 |
I/O |
5VT |
Default: PA10 Alternate: USART0_RX, TIMER0_CH2 |
|
PA11 |
103 |
I/O |
5VT |
Default: PA11 Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3 |
|
PA12 |
104 |
I/O |
5VT |
Default: PA12 Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP |
|
PA13 |
105 |
I/O |
5VT |
Default: JTMS, SWDIO Remap: PA13 |
|
NC |
106 |
|
|
- |
|
VSS_2 |
107 |
P |
|
Default: VSS_2 |
|
VDD_2 |
108 |
P |
|
Default: VDD_2 |
|
PA14 |
109 |
I/O |
5VT |
Default: JTCK, SWCLK Remap: PA14 |
|
PA15 |
110 |
I/O |
5VT |
Default: JTDI Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS |
|
PC10 |
111 |
I/O |
5VT |
Default: PC10 Alternate: UART3_TX, SDIO_D2 |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
|
Remap: USART2_TX, SPI2_SCK, I2S2_CK |
|
PC11 |
112 |
I/O |
5VT |
Default: PC11 Alternate: UART3_RX, SDIO_D3 Remap: USART2_RX, SPI2_MISO |
|
PC12 |
113 |
I/O |
5VT |
Default: PC12 Alternate: UART4_TX, SDIO_CK Remap: USART2_CK, SPI2_MOSI, I2S2_SD |
|
PD0 |
114 |
I/O |
5VT |
Default: PD0 Alternate: EXMC_D2 Remap: CAN0_RX |
|
PD1 |
115 |
I/O |
5VT |
Default: PD1 Alternate: EXMC_D3 Remap: CAN0_TX |
|
PD2 |
116 |
I/O |
5VT |
Default: PD2 Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX |
|
PD3 |
117 |
I/O |
5VT |
Default: PD3 Alternate: EXMC_CLK Remap: USART1_CTS |
|
PD4 |
118 |
I/O |
5VT |
Default: PD4 Alternate: EXMC_NOE Remap: USART1_RTS |
|
PD5 |
119 |
I/O |
5VT |
Default: PD5 Alternate: EXMC_NWE Remap: USART1_TX |
|
VSS_10 |
120 |
|
|
Default: VSS_10 |
|
VDD_10 |
121 |
|
|
Default: VDD_10 |
|
PD6 |
122 |
I/O |
5VT |
Default: PD6 Alternate: EXMC_NWAIT Remap: USART1_RX |
|
PD7 |
123 |
I/O |
5VT |
Default: PD7 Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK |
|
PG9 |
124 |
I/O |
5VT |
Default: PG9 Alternate: EXMC_NE1, EXMC_NCE2 |
|
PG10 |
125 |
I/O |
5VT |
Default: PG10 Alternate: EXMC_NCE3_0, EXMC_NE2 |
|
PG11 |
126 |
I/O |
5VT |
Default: PG11 Alternate: EXMC_NCE3_1 |
|
PG12 |
127 |
I/O |
5VT |
Default: PG12 Alternate: EXMC_NE3 |
|
PG13 |
128 |
I/O |
5VT |
Default: PG13 Alternate: EXMC_A24 |
|
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
PG14 |
129 |
I/O |
5VT |
Default: PG14 Alternate: EXMC_A25 |
|
VSS_11 |
130 |
P |
|
Default: VSS_11 |
|
VDD_11 |
131 |
P |
|
Default: VDD_11 |
|
PG15 |
132 |
I/O |
5VT |
Default: PG15 |
|
PB3 |
133 |
I/O |
5VT |
Default: JTDO Alternate:SPI2_SCK, I2S2_CK Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK |
|
PB4 |
134 |
I/O |
5VT |
Default: NJTRST Alternate: SPI2_MISO Remap: TIMER2_CH0, PB4, SPI0_MISO |
|
PB5 |
135 |
I/O |
|
Default: PB5 Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI |
|
PB6 |
136 |
I/O |
5VT |
Default: PB6 Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX |
|
PB7 |
137 |
I/O |
5VT |
Default: PB7 Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX |
|
BOOT0 |
138 |
I |
|
Default: BOOT0 |
|
PB8 |
139 |
I/O |
5VT |
Default: PB8 Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0(3) Remap: I2C0_SCL, CAN0_RX |
|
PB9 |
140 |
I/O |
5VT |
Default: PB9 Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0(3) Remap: I2C0_SDA, CAN0_TX |
|
PE0 |
141 |
I/O |
5VT |
Default: PE0 Alternate: TIMER3_ETI, EXMC_NBL0 |
|
PE1 |
142 |
I/O |
5VT |
Default: PE1 Alternate: EXMC_NBL1 |
|
VSS_3 |
143 |
P |
|
Default: VSS_3 |
|
VDD_3 |
144 |
P |
|
Default: VDD_3 |
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available in GD32F103ZF/G/I/K devices.
ARM® Cortex™-M3 core
The Cortex™-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex™-M3 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:
Internal Bus Matrix connected with I-Code bus, D-Code bus, System bus, Private Peripheral Bus (PPB) and debug accesses.
Nested Vectored Interrupt Controller (NVIC).
Flash Patch and Breakpoint (FPB).
Data Watchpoint and Trace (DWT).
Instrumentation Trace Macrocell (ITM).
Embedded Trace Macrocell (ETM).
Serial Wire JTAG Debug Port (SWJ-DP).
Trace Port Interface Unit (TPIU).
Memory Protection Unit (MPU).
On-chip memory
Up to 3072 Kbytes of Flash memory
Up to 96 Kbytes of SRAM
The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash and 96 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Table 2-4. GD32F103xx memory map shows the memory map of the GD32F103xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control unit provides a range of frequencies and clock functions. These include an Internal 8M RC oscillator (IRC8M), a High Speed crystal oscillator (HXTAL), a Low Speed Internal 40K RC oscillator (IRC40K), a Low Speed crystal oscillator (LXTAL), a Phase Lock Loop (PLL), a HXTAL clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. The frequency of AHB, APB2 and the APB1 domains can be configured by each prescaler. The maximum frequency of the AHB, APB2 and APB1 domains is 108 MHz/108 MHz/54 MHz. See Figure 2-8. GD32F103xx clock tree for details.
GD32F10x Reset Control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The system reset resets the processor core and peripheral IP components except for the SW-DP controller and the Backup domain. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), if devices are GD32F103xF/G/I/K, USART1 (PA2 and PA3) is also available for boot functions. It also can
be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option bytes.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only clock of Cortex™-M3 is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC8M, HXTAL and PLLs are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, USB Wakeup and Ethernet Wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.
Analog to digital converter (ADC)
12-bit SAR ADC
Up to 1 MSPS for 12-bit resolution
Analog input signal voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to three 12-bit multi-channel ADCs are integrated in the device. Each has a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode.
The ADCs can be triggered from the events generated by the general level 0 timers (TIMERx) or the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor generates a voltage that varies linearly with temperature. The analog supply voltage VDDA can vary from 2.6 V to 3.6 V. The output voltage of temperature sensor is internally connected to the ADC_IN16 input channel.
3.7.Digital to analog converter (DAC)
Two 12-bit DACs with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller
The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.
DMA
7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S and SDIO
The direct memory access (DMA) controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.
General-purpose inputs/outputs (GPIOs)
Up to 112 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0
~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications. The external interrupt on the GPIO pins of the device have related control and configuration registers in the Interrupt/event Controller Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardless of the AF input or output pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), input, peripheral alternate function or analog mode. Each GPIO pin can be configured as pull-up, pull-down or no pull-up/pull-down. All GPIOs are high-current capable except for analog mode.
Timers and PWM generation
Up to two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers, and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)
The advanced timer (TIMER0 & TIMER7) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 6 independent channels can be used for
Input capture
Output compare
PWM generation (edge-aligned or center-aligned counting modes)
Single pulse mode output
If configured as a general 16-bit timer, it can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, known as TIMER1 ~ TIMER4, TIMER8 ~ TIMER10, TIMER11 ~ TIMER13 can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F103xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer consists of an 8-stage prescaler and a 12-bit down-counter, it is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.
Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART4.
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F103xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.
Secure digital input and output card interface (SDIO)
Support SD2.0/SDIO2.0/MMC4.2 host interface
The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.
Universal serial bus full-speed device (USBD)
One full-speed USB Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between one or more devices. Full-speed peripheral is compliant with the USB 2.0 specification. The device controller enables 12 Mbit/s data exchange with a USB Host controller. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.
Controller area network (CAN)
One CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for USB CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and CF card
Up to 16-bit data bus
Support interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.21.Package and operation temperature
LQFP144 (GD32F103Zx), LQFP100 (GD32F103Vx), LQFP64 (GD32F103Rx), LQFP48 (GD32F103Cx) and QFN36 (GD32F103Tx)
Operation temperature range: -40°C to +85°C (industrial level)
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