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兆易創(chuàng)新GD32-GigaDevice-兆易創(chuàng)新代理

兆易創(chuàng)新GD32F205ZET6-GD32 ARM Cortex-M3 Microcontroller

兆易創(chuàng)新GD32F205ZET6-GD32 ARM Cortex-M3 Microcontroller GigaDevice Semiconductor Inc. GD32F205xx ARM? Cortex?-M3 32-bit MCU Datasheet General description The GD32F205xx device belongs to the performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM? Cortex?-M3 RISC core with best cost-performance ratio in terms of processing capacity, reduced power consumption and peripheral set. The Cortex?-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F205xx device incorporates the ARM? Cortex?-M3 32-bit processor core operating at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, a USBFS. Additional peripherals as TFT-LCD Interface (TLI) and EXMC interface with SDRAM extension support are included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F205xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, automotive navigation and so on. Device information Table 2-1. GD32F205xx devices features and peripheral list ? Part Number GD32F205xx ? RC RE RG RK VC VE VG VK Flash Fast area (KB) 256 512 384 384 256 512 384 384 ? Normal area (KB) 0 0 640 2688 0 0 640 2688 ? Total (KB) 256 512 1024 3072 256 512 1024 3072 SRAM (KB) 128 128 256 256 128 128 256 256 Timers General timer (16-bit) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) ? Advanced timer (16-bit) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) ? SysTick 1 1 1 1 1 1 1 1 ? Basic timer (16- bit) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) ? Watchdog 2 2 2 2 2 2 2 2 ? RTC 1 1 1 1 1 1 1 1 Connectivity USART 4 4 4 4 4 4 4 4 ? ? UART 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 4 (3-4,6-7) 4 (3-4,6-7) 4 (3-4,6-7) 4 (3-4,6-7) ? I2C 3 3 3 3 3 3 3 3 ? ? SPI/I2S 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) ? SDIO 1 1 1 1 1 1 1 1

產品描述

GigaDevice Semiconductor Inc.
GD32F205xx
ARM® Cortex®-M3 32-bit MCU
Datasheet

General description

The GD32F205xx device belongs to the performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best cost-performance ratio in terms of processing capacity, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F205xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, a USBFS. Additional peripherals as TFT-LCD Interface (TLI) and EXMC interface with SDRAM extension support are included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications.
The above features make GD32F205xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, automotive navigation and so on.

Device information

Table 2-1. GD32F205xx devices features and peripheral list

Part Number		GD32F205xx
		RC	RE	RG	RK	VC	VE	VG	VK
Flash	Fast area (KB)	256	512	384	384	256	512	384	384
	Normal area (KB)	0	0	640	2688	0	0	640	2688
	Total (KB)	256	512	1024	3072	256	512	1024	3072
SRAM (KB)		128	128	256	256	128	128	256	256
Timers	General timer (16-bit)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)
	Advanced timer (16-bit)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)
	SysTick	1	1	1	1	1	1	1	1
	Basic timer (16- bit)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)
	Watchdog	2	2	2	2	2	2	2	2
	RTC	1	1	1	1	1	1	1	1
Connectivity	USART	4	4	4	4	4	4	4	4
	UART	2 (3-4)	2 (3-4)	2 (3-4)	2 (3-4)	4 (3-4,6-7)	4 (3-4,6-7)	4 (3-4,6-7)	4 (3-4,6-7)
	I2C	3	3	3	3	3	3	3	3
	SPI/I2S	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)
	SDIO	1	1	1	1	1	1	1	1
	CAN	2	2	2	2	2	2	2	2
	USBFS	1	1	1	1	1	1	1	1
	TLI	0	0	0	0	1	1	1	1
GPIO		51	51	51	51	82	82	82	82
EXMC/SDRAM		0/0	0/0	0/0	0/0	1/0	1/0	1/0	1/0
ADC (CHs)		3(16)	3(16)	3(16)	3(16)	3(16)	3(16)	3(16)	3(16)
DAC		2	2	2	2	2	2	2	2

Part Number		GD32F205xx
		ZC	ZE	ZG	ZK
Flash	Code area (KB)	256	512	384	384
	Data area (KB)	0	0	640	2688
	Total (KB)	256	512	1024	3072
SRAM (KB)		128	128	256	256
Timers	General timer (16- bit)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)	10 (1-4,8-13)
	Advanced timer (16-bit)	2 (0,7)	2 (0,7)	2 (0,7)	2 (0,7)
	SysTick	1	1	1	1
	Basic timer (16- bit)	2 (5,6)	2 (5,6)	2 (5,6)	2 (5,6)
	Watchdog(16-bit)	2	2	2	2
	RTC	1	1	1	1
Connectivity	USART	4	4	4	4
	UART	4	4	4	4
	I2C	3	3	3	3
	SPI/I2S	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)	3/2 (0-2)/(1-2)
	SDIO	1	1	1	1
	CAN	2	2	2	2
	USBFS	1	1	1	1
	TLI	1	1	1	1
GPIO		114	114	114	114
EXMC/SDRAM		1/1	1/1	1/1	1/1
ADC (CHs)		3(24)	3(24)	3(24)	3(24)
DAC		2	2	2	2
Package		LQFP144

Memory map

Table 2-2 GD32F205xx memory map

Pre-defined Regions	Bus	Address	Peripherals
External Device	AHB	0xC000 0000 - 0xDFFF FFFF	EXMC - SDRAM
		0xA000 1000 - 0xBFFF FFFF	Reserved
		0xA000 0000 - 0xA000 0FFF	EXMC - SWREG
External RAM		0x9000 0000 - 0x9FFF FFFF	EXMC - PC CARD
		0x7000 0000 - 0x8FFF FFFF	EXMC - NAND
		0x6000 0000 - 0x6FFF FFFF	EXMC - NOR/PSRAM/SRAM
Peripheral	AHB2	0x5004 0000 - 0x5FFF FFFF	Reserved
	AHB1	0x5000 0000 - 0x5003 FFFF	USBFS
		0x4002 3400 - 0x4FFF FFFF	Reserved
		0x4002 3000 - 0x4002 33FF	CRC
		0x4002 2400 - 0x4002 2FFF	Reserved
		0x4002 2000 - 0x4002 23FF	FMC
		0x4002 1400 - 0x4002 1FFF	Reserved
		0x4002 1000 - 0x4002 13FF	RCU
		0x4002 0800 - 0x4002 0FFF	Reserved
		0x4002 0400 - 0x4002 07FF	DMA0
		0x4002 0000 - 0x4002 03FF	DMA1
	APB2	0x4001 8400 - 0x4001 FFFF	Reserved
		0x4001 8000 - 0x4001 83FF	SDIO
		0x4001 7800 - 0x4001 7FFF	Reserved
		0x4001 7400 - 0x4001 77FF	GPIOH
		0x4001 7000 - 0x4001 73FF	USART5
		0x4001 6C00 - 0x4001 6FFF	Reserved
		0x4001 6800 - 0x4001 6BFF	TLI
		0x4001 5800 - 0x4001 67FF	Reserved
		0x4001 5400 - 0x4001 57FF	TIMER10
		0x4001 5000 - 0x4001 53FF	TIMER9
		0x4001 4C00 - 0x4001 4FFF	TIMER8
		0x4001 4000 - 0x4001 4BFF	Reserved
		0x4001 3C00 - 0x4001 3FFF	ADC2
		0x4001 3800 - 0x4001 3BFF	USART0
		0x4001 3400 - 0x4001 37FF	TIMER7
		0x4001 3000 - 0x4001 33FF	SPI0
		0x4001 2C00 - 0x4001 2FFF	TIMER0
		0x4001 2800 - 0x4001 2BFF	ADC1
		0x4001 2400 - 0x4001 27FF	ADC0
		0x4001 2000 - 0x4001 23FF	GPIOG

Pre-defined Regions	Bus	Address	Peripherals
		0x4001 1C00 - 0x4001 1FFF	GPIOF
		0x4001 1800 - 0x4001 1BFF	GPIOE
		0x4001 1400 - 0x4001 17FF	GPIOD
		0x4001 1000 - 0x4001 13FF	GPIOC
		0x4001 0C00 - 0x4001 0FFF	GPIOB
		0x4001 0800 - 0x4001 0BFF	GPIOA
		0x4001 0400 - 0x4001 07FF	EXTI
		0x4001 0000 - 0x4001 03FF	AFIO
	APB1	0x4000 C400 - 0x4000 FFFF	Reserved
		0x4000 C000 - 0x4000 C3FF	I2C2
		0x4000 8000 - 0x4000 BFFF	Reserved
		0x4000 7C00 - 0x4000 7FFF	UART7
		0x4000 7800 - 0x4000 7BFF	UART6
		0x4000 7400 - 0x4000 77FF	DAC
		0x4000 7000 - 0x4000 73FF	PMU
		0x4000 6C00 - 0x4000 6FFF	BKP
		0x4000 6800 - 0x4000 6BFF	CAN1
		0x4000 6400 - 0x4000 67FF	CAN0
		0x4000 5C00 - 0x4000 63FF	USBFS/CAN shared
		0x4000 5800 - 0x4000 5BFF	I2C1
		0x4000 5400 - 0x4000 57FF	I2C0
		0x4000 5000 - 0x4000 53FF	UART4
		0x4000 4C00 - 0x4000 4FFF	UART3
		0x4000 4800 - 0x4000 4BFF	USART2
		0x4000 4400 - 0x4000 47FF	USART1
		0x4000 4000 - 0x4000 43FF	Reserved
		0x4000 3C00 - 0x4000 3FFF	SPI2/I2S2
		0x4000 3800 - 0x4000 3BFF	SPI1/I2S1
		0x4000 3400 - 0x4000 37FF	Reserved
		0x4000 3000 - 0x4000 33FF	FWDGT
		0x4000 2C00 - 0x4000 2FFF	WWDGT
		0x4000 2800 - 0x4000 2BFF	RTC
		0x4000 2400 - 0x4000 27FF	Reserved
		0x4000 2000 - 0x4000 23FF	TIMER13
		0x4000 1C00 - 0x4000 1FFF	TIMER12
		0x4000 1800 - 0x4000 1BFF	TIMER11
		0x4000 1400 - 0x4000 17FF	TIMER6
		0x4000 1000 - 0x4000 13FF	TIMER5
		0x4000 0C00 - 0x4000 0FFF	TIMER4
		0x4000 0800 - 0x4000 0BFF	TIMER3

Pre-defined Regions	Bus	Address	Peripherals
		0x4000 0400 - 0x4000 07FF	TIMER2
		0x4000 0000 - 0x4000 03FF	TIMER1
SRAM	AHB	0x2004 0000 - 0x3FFF FFFF	Reserved
		0x2002 0000 - 0x2003 FFFF	SRAM2(128KB)
		0x2001 C000 - 0x2001 FFFF	SRAM1(16KB)
		0x2000 0000 - 0x2001 BFFF	SRAM0(112KB)
Code	AHB	0x1FFF F810 - 0x1FFF FFFF	Reserved
		0x1FFF F800 - 0x1FFF F80F	Option Bytes
		0x1FFF B000 - 0x1FFF F7FF	System memory
		0x0830 0000 - 0x1FFF AFFF	Reserved
		0x0800 0000 - 0x082F FFFF	Main flash(3072KB)
		0x0000 0000 - 0x07FF FFFF	Aliased to flash or system memory according to BOOT pins configuration

GD32F205Zx LQFP144 pin definitions

Table 2-3. GD32F205Zx LQFP144 pin definitions

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PE2

I/O

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

PE3

I/O

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

PE4

I/O

5VT

Default: PE4 Alternate:TRACED1, EXMC_A20

Remap: TLI_B0

PE5

I/O

5VT

Default: PE5

Alternate:TRACED2, EXMC_A21 Remap: TIMER8_CH0, TLI_G0

PE6

I/O

5VT

Default: PE6

Alternate:TRACED3, EXMC_A22 Remap: TIMER8_CH1, TLI_G1

VBAT

Default: VBAT

PC13-

TAMPER- RTC

I/O

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

I/O

Default: PC14 Alternate: OSC32IN

PC15- OSC32OUT

I/O

Default: PC15 Alternate: OSC32OUT

PF0

I/O

5VT

Default: PF0

Alternate: EXMC_A0 Remap: I2C1_SDA

PF1

I/O

5VT

Default: PF1

Alternate: EXMC_A1 Remap: I2C1_SCL

PF2

I/O

5VT

Default: PF2

Alternate: EXMC_A2 Remap: I2C1_SMBA

PF3

I/O

5VT

Default: PF3

Alternate: EXMC_A3, ADC2_IN9

PF4

I/O

5VT

Default: PF4

Alternate: EXMC_A4, ADC2_IN14

PF5

I/O

5VT

Default: PF5

Alternate: EXMC_A5, ADC2_IN15

VSS_5

Default: VSS_5

VDD_5

Default: VDD_5

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
				Default: PF6
PF6	18	I/O		Alternate: ADC2_IN4, EXMC_NIORD
				Remap: TIMER9_CH0, UART6_RX
				Default: PF7
PF7	19	I/O		Alternate: ADC2_IN5, EXMC_NREG
				Remap: TIMER10_CH0, UART6_TX
				Default: PF8
PF8	20	I/O		Alternate: ADC2_IN6, EXMC_NIOWR
				Remap: TIMER12_CH0
				Default: PF9
PF9	21	I/O		Alternate: ADC2_IN7, EXMC_CD
				Remap: TIMER13_CH0
				Default: PF10
PF10	22	I/O		Alternate: ADC2_IN8, EXMC_INTR
				Remap: TLI_DE
OSCIN	23	I		Default: OSCIN Remap: PH0
OSCOUT	24	O		Default: OSCOUT Remap: PH1
NRST	25	I/O		Default: NRST
				Default: PC0
PC0	26	I/O		Alternate: ADC012_IN10
				Remap: EXMC_SDNWE
PC1	27	I/O		Default: PC1 Alternate: ADC012_IN11
				Default: PC2
PC2	28	I/O		Alternate: ADC012_IN12
				Remap: EXMC_SDNE0, SPI1_MISO
				Default: PC3
PC3	29	I/O		Alternate: ADC012_IN13
				Remap: EXMC_SDCKE0, SPI1_MOSI, I2S1_SD
VSSA	30	P		Default: VSSA
VREF-	31	P		Default: VREF-
VREF+	32	P		Default: VREF+
VDDA	33	P		Default: VDDA
				Default: PA0
PA0-WKUP	34	I/O		Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI
				Remap: UART3_TX
				Default: PA1
PA1	35	I/O		Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1
				Remap: UART3_RX
PA2	36	I/O		Default: PA2 Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2,

Pin Name	Pins	Pin Type(1)	I/O Level(2)	Functions description
				TIMER4_CH2, TIMER8_CH0, SPI0_IO3
				Default: PA3
PA3	37	I/O		Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, SPI0_IO4
				Remap: TLI_B5
VSS_4	38	P		Default: VSS_4
VDD_4	39	P		Default: VDD_4
				Default: PA4
PA4	40	I/O		Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4
				Remap: SPI2_NSS, I2S2_WS, TLI_VSYNC
				Default: PA5
PA5	41	I/O		Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
				Remap: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON
				Default: PA6
PA6	42	I/O		Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN, TIMER12_CH0
				Remap: TIMER0_BRKIN, TLI_G2
				Default: PA7
PA7	43	I/O		Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON, TIMER13_CH0
				Remap: TIMER0_CH0_ON
PC4	44	I/O		Default: PC4 Alternate: ADC01_IN14
PC5	45	I/O		Default: PC5 Alternate: ADC01_IN15
				Default: PB0
PB0	46	I/O		Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
				Remap: TIMER0_CH1_ON, TLI_R3
				Default: PB1
PB1	47	I/O		Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
				Remap: TIMER0_CH2_ON, TLI_R6
PB2	48	I/O	5VT	Default: PB2, BOOT1
PF11	49	I/O	5VT	Default: PF11 Alternate: EXMC_NIOS16, EXMC_SDNRAS
PF12	50	I/O	5VT	Default: PF12 Alternate: EXMC_A6
VSS_6	51	P		Default: VSS_6
VDD_6	52	P		Default: VDD_6
PF13	53	I/O	5VT	Default: PF13 Alternate: EXMC_A7
PF14	54	I/O	5VT	Default: PF14 Alternate: EXMC_A8
PF15	55	I/O	5VT	Default: PF15 Alternate: EXMC_A9

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

PG0

I/O

5VT

Default: PG0

Alternate: EXMC_A10

PG1

I/O

5VT

Default: PG1

Alternate: EXMC_A11

PE7

I/O

5VT

Default: PE7

Alternate: EXMC_D4, UART6_RX Remap: TIMER0_ETI

PE8

I/O

5VT

Default: PE8

Alternate: EXMC_D5, UART6_TX Remap: TIMER0_CH0_ON

PE9

I/O

5VT

Default: PE9

Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

Default: VSS_7

VDD_7

Default: VDD_7

PE10

I/O

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

PE11

I/O

5VT

Default: PE11 Alternate: EXMC_D8

Remap: TIMER0_CH1, TLI_G3

PE12

I/O

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON, TLI_B4

PE13

I/O

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2, TLI_DE

PE14

I/O

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3, TLI_PIXCLK

PE15

I/O

5VT

Default: PE15 Alternate: EXMC_D12

Remap: TIMER0_BRKIN, TLI_R7

PB10

I/O

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX

Remap: TIMER1_CH2, TLI_G4, SPI1_SCK, I2S1_CK

PB11

I/O

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3, TLI_G5

VSS_1

Default: VSS_1

VDD_1

Default: VDD_1

PB12

I/O

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS, CAN1_RX

PB13

I/O

5VT

Default: PB13

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON,

I2S1_CK, CAN1_TX

PB14

I/O

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0

PB15

I/O

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1

PD8

I/O

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX

PD9

I/O

5VT

Default: PD9

Alternate: EXMC_D14 Remap: USART2_RX

PD10

I/O

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, TLI_B3

PD11

I/O

5VT

Default: PD11 Alternate: EXMC_A16

Remap: USART2_CTS

PD12

I/O

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS

PD13

I/O

5VT

Default: PD13 Alternate: EXMC_A18

Remap: TIMER3_CH1

VSS_8

Default: VSS_8

VDD_8

Default: VDD_8

PD14

I/O

5VT

Default: PD14

Alternate: EXMC_D0 Remap: TIMER3_CH2

PD15

I/O

5VT

Default: PD15

Alternate: EXMC_D1 Remap: TIMER3_CH3

PG2

I/O

5VT

Default: PG2

Alternate: EXMC_A12

PG3

I/O

5VT

Default: PG3

Alternate: EXMC_A13

PG4

I/O

5VT

Default: PG4

Alternate: EXMC_A14, EXMC_BA0

PG5

I/O

5VT

Default: PG5

Alternate: EXMC_A15, EXMC_BA1

PG6

I/O

5VT

Default: PG6

Alternate: EXMC_INT1 Remap:TLI_R7

PG7

I/O

5VT

Default: PG7

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

Alternate: EXMC_INT2

Remap: USART5_CK, TLI_PIXCLK

PG8

I/O

5VT

Default: PG8

Alternate: EXMC_SDCLK, USART5_RTS

VSS_9

Default: VSS_9

VDD_9

Default: VDD_9

PC6

I/O

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6, USART5_TX

Remap: TIMER2_CH0, TLI_HSYNC

PC7

I/O

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7, USART5_RX

Remap: TIMER2_CH1, TLI_G6

PC8

I/O

5VT

Default: PC8

Alternate: TIMER7_CH2, SDIO_D0, USART5_CK

Remap: TIMER2_CH2

PC9

I/O

5VT

Default: PC9

Alternate: TIMER7_CH3, SDIO_D, CK_OUT1 Remap: TIMER2_CH3, I2C2_SDA

PA8

100

I/O

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF

Remap: TLI_R6, I2C2_SCL

PA9

101

I/O

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

Remap: I2C2_SMBAI

PA10

102

I/O

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

PA11

103

I/O

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

Remap: TLI_R4

PA12

104

I/O

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

Remap: TLI_R5

PA13

105

I/O

5VT

Default: JTMS, SWDIO

Remap: PA13

106

VSS_2

107

Default: VSS_2

VDD_2

108

Default: VDD_2

PA14

109

I/O

5VT

Default: JTCK, SWCLK

Remap: PA14

PA15

110

I/O

5VT

Default: JTDI

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

PC10

111

I/O

5VT

Default: PC10

Alternate: UART3_TX, SDIO_D2

Remap: USART2_TX, SPI2_SCK, I2S2_CK, TLI_R2

PC11

112

I/O

5VT

Default: PC11

Alternate: UART3_RX, SDIO_D3 Remap: USART2_RX, SPI2_MISO

PC12

113

I/O

5VT

Default: PC12

Alternate: UART4_TX, SDIO_CK

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

PD0

114

I/O

5VT

Default: PD0 Alternate: EXMC_D2

Remap: CAN0_RX, OSCIN

PD1

115

I/O

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX, OSCOUT

PD2

116

I/O

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD

PD3

117

I/O

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS, TLI_G7, SPI1_SCK, I2S1_CK

PD4

118

I/O

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

PD5

119

I/O

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

VSS_10

120

Default: VSS_10

VDD_10

121

Default: VDD_10

PD6

122

I/O

5VT

Default: PD6

Alternate: EXMC_NWAIT

Remap: USART1_RX, TLI_B2, SPI2_MOSI, I2S2_SD

PD7

123

I/O

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

PG9

124

I/O

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2 Remap: USART5_RX

PG10

125

I/O

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2 Remap: TLI_G3, TLI_B2

PG11

126

I/O

5VT

Default: PG11

Alternate: EXMC_NCE3_1 Remap: TLI_B3

PG12

127

I/O

5VT

Default: PG12

Pin Name

Pins

Pin

Type(1)

I/O

Level(2)

Functions description

Alternate: EXMC_NE3

Remap: USART5_RTS, TLI_B4, TLI_B1

PG13

128

I/O

5VT

Default: PG13

Alternate: EXMC_A24 Remap: USART5_CTS

PG14

129

I/O

5VT

Default: PG14 Alternate: EXMC_A25

Remap: USART5_TX

VSS_11

130

Default: VSS_10

VDD_11

131

Default: VDD_10

PG15

132

I/O

5VT

Default: PG15

Alternate: EXMC_SDNCAS, USART5_CTS

PB3

133

I/O

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK

PB4

134

I/O

5VT

Default: JNTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

PB5

135

I/O

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX,

EXMC_SDCKE1

PB6

136

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0

Remap: USART0_TX, CAN1_TX, EXMC_SDNE1, SPI0_IO3

PB7

137

I/O

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NL Remap: USART0_RX, SPI0_IO4

BOOT0

138

Default: BOOT0

PB8

139

I/O

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0, SDIO_D4 Remap: I2C0_SCL, CAN0_RX, TLI_B6

PB9

140

I/O

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0, SDIO_D5 Remap: I2C0_SDA, CAN0_TX, TLI_B7, SPI1_NSS,

I2S1_WS

PE0

141

I/O

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0, UART7_RX

PE1

142

I/O

5VT

Default: PE1

Alternate: EXMC_NBL1, UART7_TX

VSS_3

143

Default: VSS_3

VDD_3

144

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power.

(2)I/O Level: 5VT = 5 V tolerant.

ARM® Cortex®-M3 core

The Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M3 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)

On-chip memory

Up to 3072 Kbytes of flash memory, including code flash and data flash
Up to 256 Kbytes of SRAM

The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner flash at most, which includes code flash and data flash is available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. Up to 256 Kbytes of inner SRAM is composed of SRAM0, SRAM1, and SRAM2 that can be accessed at same time. Table 2-2 GD32F205xx memory map shows the memory map of the GD32F205xx series of devices, including flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB/APB2/APB1 domains is 120/120/60 MHz. See Figure 2-5. GD32F205xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6) and USB (PA9, PA10, PA11 and PA12). It also can be used to transfer and update the flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of flash memory is selected. It also supports to boot from bank 1 of flash memory by setting a bit in option bytes.

3.5.Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC engine with up to 2 MSPS conversion rate
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to three 12-bit 2 MSPS multi-channel ADC are integrated in the device. It is a total of up to 16 multiplexed external channels with 2 internal channels for temperature sensor and voltage reference measurement. The conversion range is between 2.6 V < VDDA < 3.6 V. An on-chip 16-bit hardware oversample scheme improves performances while off-loading the related computational burden from the MCU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally

connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

Digital to analog converter (DAC)

12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

14 channels DMA controller and each channel are configurable (7 for DMA0 and 7 for DMA1)
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S and SDIO

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 114 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 114 general purpose I/O pins (GPIO) in GD32F205xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH1 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull- up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with

digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)

The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a 16-bit general timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, known as TIMER1 ~ TIMER4, TIMER8 ~ TIMER13 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The general timer is based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. TIMER1 ~ TIMER4 and TIMER8/TIMER11 also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F205xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, it is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter.

The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source

Real time clock (RTC) and backup registers

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
84 bytes backup registers for data protection

The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
The backup registers are located in the backup domain that remains powered-on by VBAT even if VDD power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from standby mode or system reset do not affect these registers.
In addition, the backup registers can be used to implement the tamper detection, RTC calibration function and waveform detection.

Inter-integrated circuit (I2C)

Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking

for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad wire configuration available in master mode (only in SPI0)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI0.

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Up to four USARTs and four UARTs with operating frequency up to 7.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6,
UART7) are used to transmit data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI1 and SPI2
Support either master or slave mode audio
Sampling frequencies from 8 KHz up to 192 KHz are supported.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F205xx contain an I2S-bus interface that can be operated with 16/32-bit resolution in master or slave mode, pin multiplexed with SPI1 and

SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.

Universal serial bus full-speed interface (USBFS)

One USB device/host full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and PC card, SDRAM with up to 32-bit data bus
Provide ECC calculating hardware module for NAND Flash memory block
Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits Column Address, 2-bits internal banks address
SDRAM Memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)
External memory controller (EXMC) is an abbreviation of external memory controller. It is divided into several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and PC card. The EXMC also can be

configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.
The EXMC of GD32F205xx in LQFP144 package also supports synchronous dynamic random access memory (SDRAM). It translates AHB transactions into the appropriate SDRAM protocol, and meanwhile, makes sure the access time requirements of the external SDRAM devices are satisfied.

Secure digital input and output card interface (SDIO)

Support SD2.0/SDIO2.0/MMC4.2 host interface

The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.

TFT LCD interface (TLI)

24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)
Supports up to SVGA (800x600) resolution

The TFT LCD interface provides a parallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display. Two separate layers are supported in TLI, as well as layer window and blending function.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F205Zx), LQFP100 (GD32F205Vx), LQFP64 (GD32F205Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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